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Mechanism for efficient implementation of software pipelined loops in VLIW processors

  • US 8,447,961 B2
  • Filed: 02/18/2010
  • Issued: 05/21/2013
  • Est. Priority Date: 02/18/2009
  • Status: Active Grant
First Claim
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1. A system to implement a zero overhead software pipelined (SFP) loop, said system comprising:

  • a Very Long Instruction Word (VLIW) processor having a N number of execution slots, said VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size;

    a program memory that receives a Program Memory address to fetch an instruction packet, wherein said program memory is closely coupled with an instruction buffer and a dispatcher to implement said zero overhead SFP loop, wherein said zero overhead SFP loop is at least one of a short zero overhead SFP loop and a long zero overhead SFP loop, and wherein a size of said zero overhead SFP loop exceeds said instruction buffer size;

    at least one CPU control register comprising a block count and a iteration count, wherein said block count is loaded into a block counter and a last instruction address of said zero overhead SFP loop is computed to check whether said block count is greater than a maximum short block size, wherein when said block count is greater than said maximum short block size, a long SFP loop is executed, wherein when said block count is less than said maximum short block size, a short SFP loop is executed, and wherein said iteration count is loaded into an iteration counter and counts a number of iterations of said zero overhead SFP loop based on said block counter;

    a loop instruction fetch logic that tracks at least one instruction of said plurality of instructions; and

    a control logic that generates at least one of a control signals received by a instruction buffer, wherein said control signals are generated to execute said zero overhead SFP loop.

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