Stripe-based memory operation

• US 8,448,018 B2
• Filed: 09/06/2012
• Issued: 05/21/2013
• Est. Priority Date: 09/29/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/605,124
• Publication Number:
  US 20120331253A1
• Time in Patent Office: 257 Days
• Field of Search: None
• US Class Current: 714/6.22
• CPC Class Codes: G06F 11/08 Error detection or correction by redundancy in data representation, e.g. by using checking codes
• CPC Class Codes: G06F 11/1028 Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.

Claims

1. A device, comprising:

memory control circuitry configured to;

write data in a first stripe having a particular stripe size and being across a storage volume of a plurality of memory devices;

update a portion of the first stripe including;

write updated data in a portion of a second stripe, the second stripe having the particular stripe size and being across the storage volume of the plurality of memory devices; and

invalidate the portion of the first stripe; and

maintain the invalid portion of the first stripe and a remainder of the first stripe until the first stripe is reclaimed.

2. The device of claim 1, wherein the memory control circuitry is configured to split write data into a number of fragments and write the number of fragments to the plurality of memory devices by at least one of the group including:

writing at least one fragment to each of the plurality of memory devices; and

writing at least one fragment to each of a subset of the plurality of memory devices.

3. The device of claim 1, wherein the memory control circuitry is configured to update the portion of the first stripe by writing updated data in the portion of the second stripe without reading or copying the data written in the first stripe.

4. The device of claim 1, wherein the memory control circuitry is configured to maintain the first stripe by at least one of the group including:

preventing erasing of the first stripe; and

reading at least a portion of the remainder of the first stripe.

5. The device of claim 1, wherein the memory control circuitry is further configured to reclaim the first stripe, wherein reclaiming the first stripe includes:

copying the remainder of the first stripe to a third stripe in response to a wear leveling operation; and

erasing the first stripe.

6. The device of claim 1, wherein the memory control circuitry is further configured to read the portion of the second stripe on a page basis without reading the remainder of the first stripe or another portion of the second stripe.

7. A method, comprising:

writing original data in a first stripe across a storage volume of a plurality of memory devices;

updating at least a fragment of the written original data, wherein updating includes writing updated data in a second stripe without reading or copying the written original data;

calculating respective first level error correction data based on each fragment of the original data;

calculating second level error correction data based on the original data;

wherein writing the original data includes writing the original data and the first level error correction data in a first subset of the plurality of memory devices, and writing the second level error correction data in a second subset of the plurality of memory devices;

detecting an error in a fragment of original data in the first stripe, wherein the error is uncorrectable with the first level error correction data; and

correcting the error, wherein correcting the error includes;

creating replacement data for the fragment of original data based on at least a remainder of the original data and the second level error correction data in the first stripe;

writing the replacement data in a third stripe without writing the remainder of the original data in the third stripe; and

writing unrelated data in the third stripe concurrent with writing the replacement data in the third stripe, wherein the unrelated data is unrelated to the original data in the first stripe or the replacement data in the third stripe.

8. The method of claim 7, wherein the method includes reading a fragment of non-updated original data without reading a remainder of the original data.

9. The method of claim 7, wherein the second level error correction data comprises parity data.

10. The method of claim 7, wherein:

writing original data includes writing original data associated with a number of logical block addresses (LBAs); and

updating at least the fragment of the original data includes writing updated data associated with at least one of the number of LBAs.

11. A device, comprising:

memory control circuitry configured to;

write data in a stripe across a storage volume provided by a plurality of solid state memory devices across a plurality of channels;

read data from a portion of the stripe across one of the plurality of channels; and

reclaim portions of the storage volume on a stripe-basis in response to one or more of the group including;

all portions of the particular stripe having an invalid indication in a block table; and

a garbage collection threshold amount of portions of the particular stripe having an invalid indication in the block table, wherein the threshold amount of portions is greater than one and less than all portions.

12. The device of claim 11, wherein the memory control circuitry is configured to:

maintain the block table with information regarding validity of portions of the stripe;

indicate that a portion of the stripe is invalid in the block table in response to updated data corresponding to the portion of the stripe being written to another stripe; and

operate the stripe without the invalid portion.

13. The device of claim 11, wherein the memory control circuitry comprises discrete channel memory control circuitry for each of the plurality of channels.

14. The device of claim 11, wherein the memory control circuitry comprises an application specific integrated circuit (ASIC).

15. The device of claim 11, wherein the stripe comprises portions of the plurality of solid state memory devices that store the data written in the stripe.

16. A method, comprising:

writing data in a stripe across a storage volume provided by a plurality of solid state memory devices across a plurality of channels;

reading data from a portion of the stripe across one of the plurality of channels; and

reclaiming portions of the storage volume on a stripe-basis in response to one or more of the group including;

all portions of the particular stripe having an invalid indication in a block table; and

a garbage collection threshold amount of portions of the particular stripe having an invalid indication in the block table, wherein the threshold amount of portions is greater than one and less than all portions.

17. The method of claim 16, wherein the method includes:

maintaining the block table with information regarding validity of portions of the stripe;

indicating that a portion of the stripe is invalid in the block table in response to updated data corresponding to the portion of the stripe being written to another stripe; and

operating the stripe without the invalid portion.

18. The method of claim 16, wherein the method includes storing the block table in volatile memory.

19. The method of claim 18, wherein the method includes storing a copy of the block table in at least one of the plurality of solid state memory devices.

20. The method of claim 16, wherein the stripe comprises portions of the plurality of solid state memory devices that store the data written in the stripe.