Semiconductor device and method for manufacturing the same

• US 8,450,144 B2
• Filed: 03/12/2010
• Issued: 05/28/2013
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Kishida, Hideyuki, Ohara, Hiroki, Sasaki, Toshinari, Yamazaki, Shunpei
• Primary Examiner(s): MATTHEWS, COLLEEN ANN
• Application Number:
  US12/722,795
• Publication Number:
  US 20100244020A1
• Time in Patent Office: 1,173 Days
• Field of Search: 438/104, 438/151, 438/778, 257/E21.46
• US Class Current: 438/104
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

An object of an embodiment of the present invention is to provide a semiconductor device provided with a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor layer including silicon oxide, an insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain regions between the oxide semiconductor layer including silicon oxide and source and drain electrode layers. The source and drain regions are formed using a degenerate oxide semiconductor material or a degenerate oxynitride material.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a gate electrode over an insulating surface;

forming an insulating layer over the gate electrode;

forming an oxide semiconductor layer including silicon oxide over the insulating layer by a sputtering method using a first oxide semiconductor target including silicon oxide at 2.5 wt % to 20 wt % inclusive; and

forming an oxynitride layer over the oxide semiconductor layer including silicon oxide in an atmosphere including nitrogen using a second oxide semiconductor target to form a source region and a drain region.

2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing part of the oxynitride layer, which overlaps with the gate electrode so that part of the oxide semiconductor layer including silicon oxide is exposed, after forming the oxynitride layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of an electronic book, a television set, an amusement machine, and a phone.

4. A method for manufacturing a semiconductor device comprising:

forming an oxide semiconductor layer over an insulating surface by a sputtering method using a first oxide semiconductor target including silicon oxide at 2.5 wt % to 20 wt % inclusive;

forming an oxynitride layer over the oxide semiconductor layer including silicon oxide by a sputtering method using a second oxide semiconductor target in an atmosphere including nitrogen to form a source region and a drain region;

forming an insulating layer covering the oxynitride layer; and

forming a gate electrode over the insulating layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is one selected from the group consisting of an electronic book, a television set, an amusement machine, and a phone.