Graphene based switching device having a tunable bandgap

• US 8,450,198 B2
• Filed: 01/17/2012
• Issued: 05/28/2013
• Est. Priority Date: 11/04/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lin, Yu-Ming, Yau, Jeng-Bang
• Primary Examiner(s): TRAN, LONG K
• Application Number:
  US13/351,402
• Publication Number:
  US 20120115295A1
• Time in Patent Office: 497 Days
• Field of Search: 438/590, 438/142, 257/9, 257/29, 257/E29.168
• US Class Current: 438/590
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Claims

1. A method of forming a graphene-based switching device, the method comprising:

forming a template layer on a substrate, the template layer selected to facilitate single crystal growth of subsequent material formed thereupon;

patterning a resist layer on a portion of the template layer corresponding to a location of a subsequent field effect transistor (FET) channel region;

forming an amorphous layer over the template layer and patterned resist layer, and thereafter removing the patterned resist layer so as to expose the portion of the template layer corresponding to the channel region;

forming a bottom electrode layer over the amorphous layer and the exposed portion of the template layer, wherein portions of the bottom electrode layer on the template layer are crystalline in structure and electrically conductive, while portions of the bottom electrode layer on the amorphous layer are amorphous and insulating;

forming a bottom gate dielectric layer over the bottom electrode layer, wherein portions of the bottom gate dielectric layer on the crystalline bottom electrode layer are crystalline in structure and exhibit ferroelectric and piezoelectric properties, while portions of the bottom gate dielectric layer on the amorphous bottom electrode layer are amorphous, non-ferroelectric and non-piezoelectric;

forming a bi-layer graphene over the bottom gate dielectric layer;

forming source and drain contact electrodes at opposing ends of the bi-layer graphene, the bi-layer graphene defining the FET channel region;

forming a top gate dielectric layer over the bi-layer graphene; and

forming a top gate electrode over the top gate dielectric layer.

2. The method of claim 1, wherein the template layer comprises strontium titanate.

3. The method of claim 1, wherein the amorphous layer comprises titanium.

4. The method of claim 1, wherein the bottom electrode layer comprises lanthanum strontium manganite.

5. The method of claim 1, wherein the bottom gate dielectric layer comprises lead zirconate titanate.

6. The method of claim 1, wherein the top gate dielectric layer comprises an oxide selected from the group of:

Al₂O₃, SiO₂, and HfO₂.

7. The method of claim 1, wherein the source and drain contact electrodes and the top gate electrode comprise a metal selected from the group of:

gold (Au), palladium (Pd) and platinum (Pt).

8. The method of claim 1, wherein:

the template layer comprises strontium titanate;

the amorphous layer comprises titanium;

the bottom electrode layer comprises lanthanum strontium manganite;

the bottom gate dielectric layer comprises lead zirconate titanate;

the top gate dielectric layer comprises an oxide selected from the group of;

Al₂O₃, SiO₂, and HfO₂; and

the source and drain contact electrodes and the top gate electrode comprise a metal selected from the group of;

gold (Au), palladium (Pd) and platinum (Pt).

9. The method of claim 1, wherein the top and bottom gate electrodes and the bottom gate dielectric layer are configured to subject the bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene of graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

10. The method of claim 9, wherein an applied voltage across the top and bottom gate electrodes causes the bottom gate dielectric layer to expand and create the applied strain on the bi-layer graphene.