Semiconductor devices including buried gate electrodes

• US 8,450,786 B2
• Filed: 09/23/2011
• Issued: 05/28/2013
• Est. Priority Date: 09/18/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dae-Ik, Kim, Yong-Il
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US13/241,716
• Publication Number:
  US 20120007160A1
• Time in Patent Office: 613 Days
• Field of Search: 257/306, 257/E27.084
• US Class Current: 257/306
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

Claims

1. A semiconductor device comprising:

a semiconductor substrate including cell and peripheral regions;

a cell transistor in the cell region wherein the cell transistor includes a buried gate electrode in a gate trench in the substrate and first and second cell source/drain regions on opposite sides of the gate trench;

a peripheral transistor in the peripheral region, wherein the peripheral transistor includes a peripheral gate electrode on the substrate in the peripheral region and first and second peripheral source/drain regions in the substrate adjacent opposite sides of the peripheral gate electrode; and

a bit line electrically coupled to the first cell source/drain region,

wherein the bit line and a part of the peripheral gate electrode comprise a same conductive material,

wherein an upper surface of the bit line is disposed at substantially a same height above the upper surface of the semiconductor substrate as an upper surface of the peripheral gate electrode.

2. The semiconductor device of claim 1 further comprising an insulating buffer layer on the cell region, wherein the insulating buffer layer is between the bit line and the substrate,

wherein the peripheral gate electrode includes a first peripheral gate electrode layer and a second peripheral gate layer, which are sequentially stacked,

wherein the bit line and the second peripheral gate electrode layer include a same conductive material.

3. A semiconductor device comprising:

a semiconductor substrate including cell and peripheral regions;

a cell transistor in the cell region wherein the cell transistor includes a gate electrode in a gate trench in the substrate and first and second cell source/drain regions on opposite sides of the gate trench;

a peripheral transistor in the peripheral region, wherein the peripheral transistor includes a peripheral gate electrode having first and second peripheral gate electrode layers on the substrate in the peripheral region and first and second peripheral source/drain regions in the substrate adjacent opposite sides of the peripheral gate electrode, wherein the first peripheral gate electrode layer is between the second peripheral gate electrode layer and the substrate, and wherein the first and second peripheral gate electrode layers comprise different conductive materials;

an insulating buffer layer on the cell region wherein the insulating buffer layer and the first peripheral gate electrode layer comprise different materials; and

a bit line on the insulating buffer layer, wherein the bit line is electrically coupled to the first cell source/drain region through the insulating buffer layer, wherein the bit line and the second peripheral gate electrode layer comprise a same material and have a same thickness in a direction perpendicular with respect to a surface of the substrate.

4. The semiconductor device of claim 3 wherein the peripheral region is free of the insulating buffer layer.

5. The semiconductor device of claim 3 further comprising:

a buried gate capping layer in the gate trench on the buried gate electrode, wherein the buried gate capping layer is confined within the gate trench at or below the surface of the substrate.

6. The semiconductor device of claim 5 wherein a surface of the buried gate capping layer is substantially coplanar with the surface of the substrate.

7. The semiconductor device of claim 3 further comprising:

an interlayer insulating layer on the cell and peripheral regions of the substrate, wherein the insulating buffer layer is between portions of the interlayer insulating layer and the substrate; and

a capacitor electrode on the interlayer insulating layer, wherein the capacitor electrode is electrically coupled to the second cell source/drain region through the interlayer insulating layer, wherein a distance between a lower surface of the capacitor electrode and the substrate is greater than a distance between an upper surface of the bit line and the substrate.

8. The semiconductor device of claim 7 further comprising:

an insulating capping pattern on the bit line; and

a conductive pattern on the insulating capping pattern and on the interlayer insulating layer, wherein the conductive pattern is electrically coupled to the bit line through the insulating capping pattern, and wherein the conductive pattern is electrically coupled to the first peripheral source/drain region through the interlayer insulating layer.

9. The semiconductor device of claim 8 wherein a distance between an upper surface of the capacitor electrode and the substrate is greater than a distance between an upper surface of the conductive pattern and the substrate.

10. A semiconductor device comprising:

a semiconductor substrate including cell and peripheral regions;

a cell transistor in the cell region wherein the cell transistor includes a buried gate electrode in a gate trench in the substrate and first and second cell source/drain regions on opposite sides of the gate trench;

a peripheral transistor in the peripheral region, wherein the peripheral transistor includes a peripheral gate electrode having first and second peripheral gate electrode layers on the peripheral region and first and second peripheral source/drain regions in the substrate adjacent opposite sides of the peripheral gate electrode, wherein the first peripheral gate electrode layer is between the second peripheral gate electrode layer and the substrate, and wherein the first and second peripheral gate electrode layers comprise different conductive materials; and

a buried gate capping layer in the gate trench on the buried gate electrode, wherein the buried gate capping layer is confined within the gate trench at or below the surface of the substrate; and

a bit line electrically coupled to the first cell source/drain region, wherein the bit line and the second peripheral gate electrode layer comprise a same material and have a same thickness in a direction perpendicular with respect to a surface of the substrate.

11. The semiconductor device of claim 10 wherein the buried gate capping layer comprises at least one of a silicon oxide capping layer, a silicon nitride capping layer, and/or a silicon oxynitride capping layer.

12. The semiconductor device of claim 10 further comprising:

an insulating buffer layer on the cell region, wherein the insulating buffer layer is between the bit line and the substrate, wherein the insulating buffer layer and the first peripheral gate electrode layer comprise different materials, and wherein the bit line is electrically coupled to the first cell source/drain region through the insulating buffer layer.

13. The semiconductor device of claim 12 wherein the peripheral region is free of the insulating buffer layer.

14. The semiconductor device of claim 12 further comprising:

an interlayer insulating layer on the cell and peripheral regions of the substrate, wherein the insulating buffer layer is between portions of the interlayer insulating layer and the substrate, wherein a distance between an upper surface of the interlayer insulating layer and the substrate is greater than a distance between an upper surface of the bit line and the substrate; and

a capacitor electrode on the interlayer insulating layer, wherein the capacitor electrode is electrically coupled to the second cell source/drain region through the interlayer insulating layer, wherein a distance between a lower surface of the capacitor electrode and the substrate is greater than a distance between the upper surface of the bit line and the substrate.

15. The semiconductor device of claim 14 further comprising:

an insulating capping pattern on the bit line; and

a conductive pattern on the insulating capping pattern and on the interlayer insulating layer, wherein the conductive pattern is electrically coupled to the bit line through the insulating capping pattern, and wherein the conductive pattern is electrically coupled to the first peripheral source/drain region through the interlayer insulating layer.

16. The semiconductor device of claim 15 wherein a distance between an upper surface of the capacitor electrode and the substrate is greater than a distance between an upper surface of the conductive pattern and the substrate.

17. The semiconductor device of claim 10 wherein a surface of the buried gate capping layer is substantially coplanar with the surface of the substrate.

18. A semiconductor device comprising:

a semiconductor substrate including cell and peripheral regions;

a cell transistor in the cell region wherein the cell transistor includes a buried gate electrode in a gate trench in the substrate and first and second cell source/drain regions on opposite sides of the gate trench;

a peripheral transistor in the peripheral region, wherein the peripheral transistor includes a peripheral gate electrode having first and second peripheral gate electrode layers on the peripheral region and first and second peripheral source/drain regions in the substrate adjacent opposite sides of the peripheral gate electrode, wherein the first peripheral gate electrode layer is between the second peripheral gate electrode layer and the substrate, and wherein the first and second peripheral gate electrode layers comprise different conductive materials;

an insulating buffer layer on the cell region;

a bit line on the insulating buffer layer, wherein the bit line is electrically coupled to the first cell source/drain region through the insulating buffer layer;

an interlayer insulating layer on the cell and peripheral regions of the substrate, wherein the insulating buffer layer is between portions of the interlayer insulating layer and the substrate;

a capacitor electrode on the interlayer insulating layer, wherein the capacitor electrode is electrically coupled to the second cell source/drain region through the interlayer insulating layer;

an insulating capping pattern on the bit line; and

a conductive pattern on the insulating capping pattern and on the interlayer insulating layer, wherein the conductive pattern is electrically coupled to the bit line through the insulating capping pattern, and wherein the conductive pattern is electrically coupled to the first peripheral source/drain region through the interlayer insulating layer;

wherein a distance between an upper surface of the capacitor electrode and the substrate is greater than a distance between an upper surface of the conductive pattern and the substrate.

19. The semiconductor device of claim 18 wherein the bit line and the second peripheral gate electrode layer comprise a same material and have a same thickness in a direction perpendicular with respect to a surface of the substrate.

20. The semiconductor device of claim 18 wherein the peripheral region is free of the insulating buffer layer.

21. The semiconductor device of claim 18 further comprising:

a buried gate capping layer in the gate trench on the buried gate electrode, wherein the buried gate capping layer is confined within the gate trench at or below a surface of the substrate.

22. The semiconductor device of claim 21 wherein a surface of the buried gate capping layer is substantially coplanar with a surface of the substrate.

23. The semiconductor device of claim 18 wherein the insulating buffer layer and the first peripheral gate electrode layer comprise different materials.