MOS device with varying contact trench lengths

• US 8,450,794 B2
• Filed: 12/09/2011
• Issued: 05/28/2013
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin, Pan, Ji, Wei, Sung-Po
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US13/316,365
• Publication Number:
  US 20120080751A1
• Time in Patent Office: 536 Days
• Field of Search: 257/328
• US Class Current: 257/328
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is formed on a semiconductor substrate. The device comprises a drain; an epitaxial layer overlaying the drain; a body disposed in the epitaxial layer, having a body top surface and a body bottom surface; a source embedded in the body, extending from the body top surface into the body; a first gate trench extending into the epitaxial layer; a first gate disposed in the first gate trench; an active region contact trench extending through the source and at least part of the body into the drain; an active region contact electrode disposed within the active region contact trench; a second gate trench extending into the epitaxial layer; a second gate disposed in the gate trench; a gate contact trench formed within the second gate; and a gate contact electrode disposed within the gate contact trench.

Claims

1. A semiconductor device formed on a semiconductor substrate, comprising:

an epitaxial layer overlaying the semiconductor substrate;

a drain formed on back of the semiconductor substrate;

a drain region that extends into the epitaxial layer; and

a body disposed in the epitaxial layer, having a body top surface and a body bottom surface;

a source embedded in the body, extending from the body top surface into the body;

a first gate trench extending into the epitaxial layer;

a first gate disposed in the first gate trench;

an active region contact trench extending through the source and at least part of the body into the drain region;

an active region contact electrode disposed within the active region contact trench;

a second gate trench extending into the epitaxial layer;

a second gate disposed in the second gate trench;

a gate contact trench formed within the second gate; and

a gate contact electrode disposed within the gate contact trench.

2. The semiconductor device of claim 1, wherein the gate contact trench has a different depth than the active region contact trench.

3. The semiconductor device of claim 1, wherein the active region contact electrode and the drain region form a Schottky diode.

4. The semiconductor device of claim 1, further comprising a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench.

5. The semiconductor device of claim 1, further comprising an anti-punch through implant disposed on a sidewall of the active region contact trench.

6. The semiconductor device of claim 1, further comprising a blanket implant deposited throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer.

7. The semiconductor device of claim 1, further comprising an epitaxial layer profile tuning implant deposited under the active region contact trench.

8. The semiconductor device of claim 1, further comprising an island region below the active region contact trench, wherein the island region has opposite polarity as the epitaxial layer.

9. The semiconductor device of claim 1, wherein the first gate and the second gate extend above the body top surface.