Semiconductor structure with a planar Schottky contact

• US 8,450,798 B2
• Filed: 10/21/2011
• Issued: 05/28/2013
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Session, Fred
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US13/279,107
• Publication Number:
  US 20120098061A1
• Time in Patent Office: 585 Days
• Field of Search: 257/284, 257/334, 257/267, 257/280, 257/471, 257/E21.158, 257/E27.068
• US Class Current: 257/334
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the top surface of the semiconductor layer adjacent the trench so as to form a Schottky contact with the top surface of the semiconductor layer adjacent the trench. A surface of the semiconductor layer in the Schottky region is lower relative to a surface of the semiconductor layer in the FET region.

Claims

1. A semiconductor structure, comprising:

a field effect transistor (FET) trench in a FET region of a semiconductor layer, the FET trench having a FET conductive electrode therein, the FET conductive electrode having a top surface recessed relative to a top surface of a source region associated with the FET trench in the FET region; and

a Schottky trench in a Schottky region of the semiconductor layer, the Schottky trench having a Schottky conductive electrode therein, the Schottky conductive electrode in the Schottky trench having a top surface substantially coplanar with a top surface of a mesa region in the Schottky region, the top surface of the mesa region forming at least a portion of a Schottky contact, the top surface of the source region of the FET region being higher than the top surface of the mesa region of the Schottky region.

2. The semiconductor of claim 1, wherein the FET region of the semiconductor layer includes a trench FET and the Schottky region of the semiconductor layer includes a rectifier.

3. The semiconductor of claim 1, the FET region comprising:

a well region extending into the semiconductor layer, the source region being disposed in the well region adjacent the FET trench, the source region and the well region being of opposite conductivity type;

a heavy body region disposed in the well region, the heavy body region being of a same conductivity type but a higher doping concentration than the well region; and

an interconnect layer electrically contacting the source region and the heavy body region.

4. The semiconductor of claim 1, wherein the FET region includes a trench insulated-gate bipolar transistor (IGBT),

the semiconductor layer including:

an epitaxial layer extending over a substrate, the epitaxial layer having a lower doping concentration than the substrate, and

a well region extending into the substrate and having a conductivity type opposite a conductivity type of the epitaxial layer, the well region and the substrate having a same conductivity type.

5. The semiconductor of claim 1, the FET trench comprising:

a shield dielectric layer lining a lower sidewall and a bottom region of the FET trench;

a shield electrode disposed in the bottom region of the FET trench;

an inter-electrode dielectric layer disposed on top of the shield electrode;

a gate dielectric layer lining an upper sidewall of the FET trench, the gate dielectric layer being thinner than the shield dielectric layer; and

a gate electrode disposed on top of the inter-electrode dielectric layer.

13. The semiconductor structure of claim 1, wherein the FET trench includes a dielectric layer lining a sidewall of the FET trench.

14. The semiconductor structure of claim 1, wherein the Schottky trench includes only one conductive electrode.

15. The semiconductor structure of claim 1, wherein the FET region includes:

a dielectric layer lining a sidewall of the FET trench and a bottom region of the FET trench, the dielectric layer being thicker along the bottom region than along the sidewall.

6. A trench MOS barrier Schottky (TMBS) rectifier, comprising:

a trench extending into a semiconductor layer,

a dielectric layer lining a sidewall of the trench;

a conductive electrode having a top surface coplanar with a top surface of the semiconductor layer adjacent the trench; and

an interconnect layer including a conformal barrier metal layer which contacts the top surface of the semiconductor layer so as to form a Schottky contact with the top surface of the semiconductor layer, the conformal barrier layer extending over and directly contacting at least a portion of the conductive electrode.

7. The TMBS rectifier of claim 6, further comprising:

a second conductive electrode having a top surface coplanar with the top surface of the semiconductor layer adjacent the trench, the conformal barrier metal layer directly contacting both the conductive electrode and the second conductive electrode.

8. The TMBS rectifier of claim 6, wherein the conformal barrier metal layer is substantially planar.

9. The TMBS rectifier of claim 6, further comprising:

a second conductive electrode having a top surface coplanar with the top surface of the semiconductor layer adjacent the trench, the second conductive electrode having a top surface coplanar with the top surface of the semiconductor layer.

10. The TMBS rectifier of claim 6, wherein the interconnect layer includes a metal layer over and directly in contact with the conformal barrier layer.

16. The TMBS rectifier of claim 6, wherein the conductive electrode is disposed within the trench.

17. The TMBS rectifier of claim 6, further comprising:

a field effect transistor (FET) region; and

a Schottky region including;

the trench, the dielectric layer, and the conductive electrode, the FET region having a top surface of a source region being higher than a top surface of a mesa region of the Schottky region.

18. The TMBS rectifier of claim 17, wherein the Schottky region includes only one conductive electrode.

19. The TMBS rectifier of claim 17, wherein the FET region including:

a FET trench extending into the semiconductor layer; and

a dielectric layer lining a sidewall of the FET trench and a bottom region of the FET trench, the dielectric layer being thicker along the bottom region than along the sidewall.

11. A trench MOS barrier Schottky (TMBS) rectifier comprising:

a trench extending into a semiconductor layer;

a dielectric layer lining a sidewall of the trench;

a conductive electrode having a top surface that is coplanar with a top surface of the semiconductor layer adjacent the trench; and

an interconnect layer comprising a conformal barrier metal layer contacting the top surface of the semiconductor layer so as to form a Schottky contact with the top surface of the semiconductor layer, the conformal barrier layer extending over and directly contacting the conductive electrode, a top surface of the conductive electrode being substantially coplanar with a top surface of the semiconductor layer such that the conformal barrier metal layer is substantially planar.

12. The TMBS rectifier of claim 11, wherein the interconnect layer comprises a metal layer over and directly in contact with the conformal barrier layer.

20. The TMBS rectifier of claim 11, further comprising:

a Schottky region; and

a field effect transistor (FET) region having a top surface of a source region higher than a top surface of a mesa region of the Schottky region.

21. The TMBS rectifier of claim 11, further comprising a FET region including:

a FET trench extending into the semiconductor layer;

a FET shield dielectric layer lining a lower sidewall and a bottom region of the FET trench;

a FET shield electrode disposed in the bottom region of the FET trench;

a FET inter-electrode dielectric layer disposed over the shield electrode;

a FET gate dielectric layer lining an upper sidewall of the FET trench, the FET gate dielectric layer being thinner than the FET shield dielectric layer; and

a FET gate electrode disposed over the FET inter-electrode dielectric layer.

22. The TMBS rectifier of claim 11, further comprising:

a Schottky region including the trench, the dielectric layer, and the conductive electrode; and

a shield electrode disposed in a bottom region of the trench.