Semiconductor device and structure for heat removal

• US 8,450,804 B2
• Filed: 08/10/2012
• Issued: 05/28/2013
• Est. Priority Date: 03/06/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US13/571,614
• Publication Number:
  US 20120306082A1
• Time in Patent Office: 291 Days
• Field of Search: 257/347, 257/758, 257/747, 257712-718, 257/E27.064, 257/E23.051
• US Class Current: 257/347
• CPC Class Codes: H01L 2027/11812 4-T CMOS basic cell
• CPC Class Codes: H01L 2027/11874 Layout specification, i.e. inner core region
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.

Claims

1. A device, comprising:

a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, the said second layer overlaying said interconnection layer, wherein said second layer is less than about 0.4 micron thick, wherein said second layer has a coefficient of thermal expansion; and

a connection path connecting said second transistors to said interconnection layer, wherein said connection path comprises at least one through-layer via, and said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of said second layer coefficient of thermal expansion.

2. A device according to claim 1, wherein said through-layer via comprises tungsten.

3. A device according to claim 1, wherein said connection path comprises copper or aluminum.

4. A device according to claim 1, further comprising:

a thermal connection to at least one of said second transistors, wherein said thermal connection is electrically isolated from said at least one of said second transistors, and

said thermal connection provides a thermally conductive path between said at least one of said second transistors and the top or bottom surface of said device, and

said thermally conducting path has a thermal conductivity of at least 100 W/m-K.

5. A device according to claim 1, wherein said first layer comprises at least one alignment mark, and at least one said through-layer via is aligned at least partially to said first alignment mark with less than 10 nm alignment error.

6. A mobile phone comprising the device of claim 1.

7. A device according to claim 1, wherein said interconnection layer comprises a power grid to provide power to at least one of said second transistors.

8. A device, comprising:

a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum; and

a second layer comprising second transistors, the said second layer overlaying said interconnection layer, wherein

said second layer is less than about 0.4 micron thick, and

said interconnection layer comprises a power grid to provide power to at least one of said second transistors.

9. A device according to claim 8, further comprising logic cells comprising second transistors, wherein at least one of said logic cells comprises a connection made by said interconnection layer.

10. A device according to claim 8, further comprising a connection path between said second transistors and said interconnection layer, wherein

said connection path comprises at least one through-layer via, and said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of a coefficient of thermal expansion of said second layer.

11. A device according to claim 8, wherein said first layer comprises a first alignment mark, and at least one via through said second layer, and said at least one via comprises alignment at least partially to said first alignment mark.

12. A device according to claim 11, wherein said at least one via comprises tungsten.

13. A device according to claim 8, comprising:

a thermal connection to at least one of said second transistors, wherein said thermal connection is electrically isolated from said at least one of said second transistors, and

said thermal connection provides a thermally conductive path between said at least one of said second transistors and the top or bottom surface of said device, and

said thermally conducting path has a thermal conductivity of at least 100 W/m-K.

14. A device, comprising:

a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, said second layer overlaying said interconnection layer, wherein said second layer is less than about 0.4 micron thick; and

a thermal connection to at least one of said second transistors, wherein

said thermal connection is electrically isolated from said at least one of said second transistors, and

said thermal connection provides a thermally conductive path between said at least one of said second transistors and the top or bottom surface of said device.

15. A device according to claim 14, wherein the top or bottom surface of said device comprises a heat sink.

16. A mobile phone comprising the device of claim 14.

17. A device according to claim 14, wherein said thermally conducting path has a thermal conductivity of at least 100 W/m-K.

18. A device according to claim 14, wherein said thermal connection comprises a reverse biased p-n junction.

19. A device according to claim 14, wherein said interconnection layer comprises a power grid to provide power to at least one of said second transistors.

20. A device according to claim 14, further comprising

a connection path connecting said second transistors to said interconnection layer, wherein

said connection path comprises at least one through-layer via, and said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of said second layer coefficient of thermal expansion.

21. A device according to claim 14, wherein said first layer comprises a first alignment mark, and at least one of said second transistors is aligned to said first alignment mark.

22. A device according to claim 14, further comprising:

logic cells comprising said second transistors, wherein at least one of said logic cells comprises a connection made by said interconnection layer.

23. A device, comprising:

a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum;

a second layer comprising second transistors, said second layer overlaying said interconnection layer, wherein said second layer is less than 0.4 micron thick; and

a plurality of thermally conducting paths from said second transistors to a heat sink, wherein

at least one of said thermally conducting paths has a thermal conductivity of at least 100 W/m-K, and

wherein the power delivery paths to at least one of said second transistors comprises said thermally conducting paths.

24. A device according to claim 23, wherein said thermally conducting paths comprise a heat spreader layer between said first layer and said second layer.

25. A device according to claim 23, wherein at least one of said thermal conducting paths comprises a thermal connection to said second layer, and

said thermal connection is electrically non-conducting.

26. A mobile system comprising the device of claim 23.

27. A device according to claim 23, wherein at least one of said second transistors has at least three sides, and thermally conductive dielectric regions are located on the at least three sides.

28. A device according to claim 23, wherein said thermal connection comprises a biased p-n junction.

29. A device according to claim 23, wherein said interconnection layer comprises a power grid to provide power to at least one of said second transistors.

30. A device according to claim 23, further comprising:

a connection path connecting said second transistors to said interconnection layer, wherein

said connection path comprises at least one through-layer via, and

said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of said second layer coefficient of thermal expansion.