Semiconductor device and structure for heat removal
First Claim
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1. A device, comprising:
- a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum;
a second layer comprising second transistors, the said second layer overlaying said interconnection layer, wherein said second layer is less than about 0.4 micron thick, wherein said second layer has a coefficient of thermal expansion; and
a connection path connecting said second transistors to said interconnection layer, wherein said connection path comprises at least one through-layer via, and said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of said second layer coefficient of thermal expansion.
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Abstract
A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.
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Citations
30 Claims
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1. A device, comprising:
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a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum; a second layer comprising second transistors, the said second layer overlaying said interconnection layer, wherein said second layer is less than about 0.4 micron thick, wherein said second layer has a coefficient of thermal expansion; and a connection path connecting said second transistors to said interconnection layer, wherein said connection path comprises at least one through-layer via, and said through-layer via comprises material whose co-efficient of thermal expansion is within about 50 percent of said second layer coefficient of thermal expansion. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device, comprising:
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a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum; and a second layer comprising second transistors, the said second layer overlaying said interconnection layer, wherein said second layer is less than about 0.4 micron thick, and said interconnection layer comprises a power grid to provide power to at least one of said second transistors. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A device, comprising:
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a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum; a second layer comprising second transistors, said second layer overlaying said interconnection layer, wherein said second layer is less than about 0.4 micron thick; and a thermal connection to at least one of said second transistors, wherein said thermal connection is electrically isolated from said at least one of said second transistors, and said thermal connection provides a thermally conductive path between said at least one of said second transistors and the top or bottom surface of said device. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A device, comprising:
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a first layer of first transistors, overlaid by at least one interconnection layer, wherein said interconnection layer comprises copper or aluminum; a second layer comprising second transistors, said second layer overlaying said interconnection layer, wherein said second layer is less than 0.4 micron thick; and a plurality of thermally conducting paths from said second transistors to a heat sink, wherein at least one of said thermally conducting paths has a thermal conductivity of at least 100 W/m-K, and wherein the power delivery paths to at least one of said second transistors comprises said thermally conducting paths. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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Specification