Methods of forming spin torque devices and structures formed thereby

• US 8,450,818 B2
• Filed: 06/18/2009
• Issued: 05/28/2013
• Est. Priority Date: 06/18/2009
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nikonov, Dmitri E., Bourianoff, George I., Jacob, Ajey P.
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US12/456,581
• Publication Number:
  US 20100321993A1
• Time in Patent Office: 1,440 Days
• Field of Search: 365/63, 365/66, 365/100, 365/158, 257421-425
• US Class Current: 257/421
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3268 the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
• CPC Class Codes: H01F 10/3286 Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H03K 19/18 using galvano-magnetic devices, e.g. Hall-effect devices
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Methods of forming spin torque microelectronic devices are described. Those methods may include forming a free FM layer on a substrate, forming a non-magnetic layer on the free FM layer, forming at least three input pillars on the non-magnetic layer, and forming an output pillar on the non-magnetic layer to form a majority gate device.

Claims

1. A structure comprising:

a free FM layer disposed on a substrate;

a non-magnetic layer disposed on the free FM layer;

at least three input pillars disposed on the non-magnetic layer; and

an output pillar disposed on the non-magnetic layer,

wherein each of the at least three input pillars and the output pillar comprise a first fixed FM layer disposed on the non-magnetic layer, an exchange layer disposed on the first fixed FM layer, and a second fixed FM layer disposed on the exchange layer, and a contact disposed on the second fixed FM layer.

2. The structure of claim 1 further comprising electrical contacts disposed on the at least three input pillars and the output pillar.

3. The structure of claim 1 wherein the at least three input pillars and the output pillar each comprise two fixed FM layers separated by an exchange layer, wherein current is capable of being passed through one of the fixed FM layers of the output pillar and the free FM layer.

4. The structure of claim 1 wherein the structure comprises a majority gate device capable of performing at least one logic operation by switching a magnetization state in the free FM layer.

5. The structure of claim 4 wherein the majority gate device comprises at least one of a dynamically reconfigurable logic gate and a non-volatile logic gates.

6. A majority gate device comprising;

a free FM layer disposed on a metal layer;

a non-magnetic layer disposed on the free FM layer;

at least three input pillars disposed on the non-magnetic layer, wherein the at least three input pillars comprise a first fixed FM layer disposed on the non-magnetic layer, an exchange layer disposed on the first fixed FM layer, and a second fixed FM layer disposed on the exchange layer; and

an output pillar disposed on the non-magnetic layer, wherein the output pillar comprises a first fixed FM layer disposed on the non-magnetic layer, an exchange layer disposed on the first fixed FM layer, and a second fixed FM layer disposed on the exchange layer.

7. The majority gate device of claim 6 further comprising electrical contacts disposed on the second fixed FM layers of the at least three input pillars and the output pillar.

8. The majority gate device of claim 6 wherein the non-magnetic layer comprises a tunneling dielectric material.

9. The majority gate device of claim 6 further comprising wherein voltages are capable of being applied to the at least three input pillars and a current is capable of being sensed in the output pillar that is dependent on a magnetization state of the free FM layer.

10. The majority gate device of claim 6 wherein the device is capable of performing at least one logic operation by switching a magnetization state in the free FM layer.

11. The majority logic gate of claim 6 wherein the majority logic gate comprises at least one of a dynamically reconfigurable logic gate and a non-volatile logic gates.

12. The majority logic gate of claim 6 wherein a computational variable of the majority gate device is encoded as a direction of magnetization.

13. The majority logic gate of claim 6 further comprising a system, wherein a bus is communicatively coupled to the majority logic gate, and a DRAM is communicatively coupled to the bus.