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Charge control circuit and charge controlling semiconductor integrated circuit

  • US 8,450,982 B2
  • Filed: 03/23/2009
  • Issued: 05/28/2013
  • Est. Priority Date: 03/24/2008
  • Status: Active Grant
First Claim
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1. A charge controlling semiconductor integrated circuit, comprising:

  • a current controlling transistor provided between a voltage input terminal and an output terminal;

    a control circuit which controls the current controlling transistor to control a charging current to be supplied to a secondary battery; and

    a chip temperature detection circuit provided with a temperature detecting element to detect a chip temperature, the chip temperature detection circuit outputting a voltage according to a detected temperature,wherein the control circuit controls the current controlling transistor so as to;

    (i) decrease the charging current in accordance with an increase in the chip temperature when the chip temperature is within a predetermined temperature range lower than a set temperature of breaking the charging current;

    (ii) flow the charging current having a predetermined current value when the chip temperature is lower than a lower limit temperature of the temperature range; and

    (iii) flow the charging current having a value smaller than the predetermined current value when the chip temperature is within a range from an upper limit temperature of the temperature range to the set temperature of breaking the charging current, andwherein the chip temperature detection circuit includes;

    a subtraction circuit which subtracts a voltage generated by the temperature detecting element from a predetermined voltage;

    an inverting amplifying circuit which performs inverting amplification of an output of the subtraction circuit;

    a first comparator which compares an output of the inverting amplifying circuit with a first voltage;

    a first selection section controlled by an output of the first comparator to selectively transmit either of the output of the inverting amplifying circuit and the first voltage to a subsequent stage, the first selection section outputting the output of the inverting amplifying circuit when the output of the inverting amplifying circuit is lower than the first voltage and outputting the first voltage when the output of the inverting amplifying circuit is higher than the first voltage;

    a second comparator which compares the output of the inverting amplifying circuit with a second voltage lower than the first voltage; and

    a second selection section controlled by an output of the second comparator to selectively transmit either of the output of the inverting amplifying circuit and the second voltage to a subsequent stage, the second selection section outputting the output of the inverting amplifying circuit when the output of the inverting amplifying circuit is higher than the second voltage and outputting the second voltage when the output of the inverting amplifying circuit is lower than the second voltage.

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