Advanced repeater with duty cycle adjustment

• US 8,451,025 B2
• Filed: 09/19/2011
• Issued: 05/28/2013
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Scott Pitkethly
• Original Assignee: Scott Pitkethly
• Inventors: Pitkethly, Scott
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US13/236,554
• Publication Number:
  US 20120242387A1
• Time in Patent Office: 617 Days
• Field of Search: 326/86, 326/85, 326/87, 326/91, 326/27, 326/29, 326/83, 327/175, 327/178
• US Class Current: 326/86
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Claims

1. A circuit comprising:

first circuitry configured to drive an output signal responsive to an input signal;

second circuitry configured to selectably adjust a duty cycle of said output signal, wherein a drive level of said first circuitry is independent of said duty cycle; and

third circuitry configured to produce a delayed version of said input signal, characterized by a delay that is greater than a transition time of said first circuitry less a delay of said second circuitry.

2. The circuit of claim 1 wherein said output signal is inverted relative to said input signal.

3. The circuit of claim 1 wherein said third circuitry is free of discrete components.

4. The circuit of claim 1 wherein said delayed version of said input signal is operable for changing a drive level of said output signal.

5. The circuit of claim 1 wherein a first state of said first circuitry comprises a high level drive circuit and a second state of said first circuitry comprises a substantially weaker level drive circuit.

6. The circuit of claim 5 wherein said substantially weaker level drive circuit comprises substantially no drive.

7. The circuit of claim 5 wherein said second state of said first circuitry comprises circuitry configured to implement a keeper mode.

8. The circuit of claim 1 wherein said input signal originates from a microprocessor clock signal.

9. The circuit of claim 1 wherein said output signal propagates through a maximum of three sequential devices.

10. A method comprising:

receiving a transition of an input signal at a circuit input;

responsive to a plurality of control signals, selectively adjusting a rise or a fall time of an output signal generally corresponding to said input signal;

driving an output level corresponding to said transition, wherein said output level is independent of said rise or said fall time; and

ceasing said driving prior to an arrival of a subsequent transition of said input signal.

11. The method of claim 10 further comprising weakly holding said output signal line in a present state subsequent to said ceasing.

12. The method of claim 10 wherein said driving comprises driving for a duration that is sufficient for driving said output signal line to a desired level.

13. The method of claim 10 wherein said output signal line is inverted relative to said circuit input.

14. The method of claim 10 wherein said ceasing comprises changing a state of combinatorial logic.

15. The method of claim 10 further comprising propagating said input signal to said output level through no more than three sequential devices.

16. A circuit comprising:

first circuitry configured to drive a rising edge transition on an output signal line;

second circuitry configured to drive a falling edge transition on said output signal line;

third circuitry configured to selectably adjust timing of said rising edge transition,

fourth circuitry configured to selectably adjust timing of said falling edge transition, and

wherein a drive level of said output signal line does not affect said timing of said rising edge transition.

17. The circuit of claim 16 wherein a drive level of said output signal line does not affect said timing of said falling edge transition.

18. The circuit of claim 16 wherein said third circuitry comprises an OR gate.

19. The circuit of claim 16 wherein said forth circuitry comprises an AND gate.

20. The circuit of claim 16 wherein a transition propagates through a maximum of three sequential devices from an input signal line to said output signal line.