Data interface circuit

• US 8,451,147 B2
• Filed: 10/18/2010
• Issued: 05/28/2013
• Est. Priority Date: 07/16/2010
• Status: Expired due to Fees

• Current Assignee: MS Ramaiah School of Advanced Studies
• Original Assignee: MS Ramaiah School of Advanced Studies
• Inventors: Mazumdar, Dipayan, Raj, Cyril P
• Primary Examiner(s): Mai, Lam T
• Application Number:
  US13/320,368
• Publication Number:
  US 20120235839A1
• Time in Patent Office: 953 Days
• Field of Search: 341 50- 90, 375/257, 379/93.07, 379/93.28, 455/557, 398/45, 398/52, 398/83, 709/233, 709/236, 370/201, 370/229, 370/216, 370/218, 370/119, 370/381, 370/401, 370/437, 370/429, 370/213, 370/386, 370/396, 370/422
• US Class Current: 341/50
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane

Abstract

In an illustrative embodiment, a data interface circuit is provided. The data interface circuit comprises data sources, input blocks, a space switch, output blocks and a multi-core processor. The data interface circuit allows data provided in different voltage ranges and sampling frequencies to be transmitted to the appropriate core in the multi-core processor via the switch. Data conversion elements in the input blocks convert data from the data sources and having varying voltage ranges and sampling frequencies into data having a voltage range and sampling frequency suitable for the space switch. Analogously, data conversion elements in the output blocks convert data from the space switch into data having a voltage range and sampling frequency suitable for the corresponding core in the multi-core processor. In one embodiment, level shifters and FIFO buffers are used in the input blocks and output blocks.

Claims

1. An integrated circuit comprising:

a switching block configured to route received data to an output, the output selected from a plurality of outputs;

an input data interface configured to be coupled to the switching block and further configured to;

receive input data,

convert the input data into a form compatible for the switching block,

convert a voltage level of the input data to a voltage level compatible for the switching block, and

provide the converted data to the switching block; and

an output data interface configured to be coupled to the switching block and configured to;

receive routed data from the switching block,

convert the routed data into a form compatible for the selected output,

convert a voltage level of the routed data to a voltage level compatible for the selected output, and

provide output data to the selected output.

2. The integrated circuit of claim 1, wherein the input data interface is further configured to convert a frequency of the input data to a frequency compatible for the switching block, and wherein the output data interface is further configured to convert a frequency of the routed data to a frequency compatible for the selected output.

3. The integrated circuit of claim 2, wherein the input data interface comprises:

a first-in first-out (FIFO) buffer configured to convert the frequency of the input data to the frequency compatible for the switching block, and

a voltage level shifter configured to convert the voltage level of the input data to the voltage level compatible for the switching block.

4. The integrated circuit according to claim 3, wherein the FIFO buffer is further configured to convert the frequency of the input data to the frequency compatible for the switching block by adjustment of a data rate of the input data to a data rate compatible for the switching block.

5. The integrated circuit of claim 3, wherein the FIFO buffer comprises a distributed FIFO buffer comprising one or more sub-blocks, the one or more sub-blocks occupying different physical locations on a silicon die comprising one or more memory locations.

6. The integrated circuit of claim 3, wherein the voltage level shifter is configured in a single ended mode and configured to convert unipolar or bipolar digital signals to voltage levels compatible with the FIFO buffer.

7. An integrated circuit comprising:

a space switch configured to route received data to an output, the output selected from a plurality of outputs;

a plurality of input interfaces configured to receive input data, each input interface comprising an input voltage level shifter and an input distributed first-in first-out (FIFO) element interconnected by segments of interconnects, wherein the input voltage level shifter is configured to convert a voltage level of the input data to a voltage level compatible for the space switch, and wherein the input distributed FIFO element is configured to convert a frequency of the input data to a frequency compatible for the space switch; and

an output interface configured to receive routed data from the space switch and to provide output data to the selected output, the output interface comprising an output voltage shifter coupled in series to an output distributed FIFO element, wherein the output voltage shifter is configured to convert a voltage level of the routed data to a voltage level compatible for the selected output, and wherein the output distributed FIFO element is configured to convert a frequency of the routed data to a frequency compatible for the selected output.

8. The integrated circuit of claim 7, wherein the input distributed FIFO element and the output distributed FIFO element are implemented on an active layer of silicon of a two dimensional integrated circuit.

9. The integrated circuit of claim 7, wherein the input distributed FIFO element and the output distributed FIFO element are implemented on different layers of a three-dimensional silicon integrated circuit.

10. The integrated circuit of claim 7, further comprising a second space switch coupling the input interfaces to the output interface, the second space switch configured to route data to the output, wherein the second space switch is activated to replace the space switch if the space switch fails.

11. The integrated circuit of claim 7, wherein the space switch comprises a fixed point space switch.

12. The integrated circuit of claim 7, wherein the space switch comprises a floating point space switch.

13. The integrated circuit of claim 7, wherein the space switch comprises a multi-stage cross bar shuffle exchange.

14. The integrated circuit of claim 7, wherein the output interface further comprises a reorder buffer coupled in series to the output voltage shifter and the output distributed FIFO element, and wherein the reorder buffer is configured to reorder a first sequence of the routed data to be in a second sequence compatible for the selected output.

15. The integrated circuit of claim 14, wherein the reorder buffer comprises one input port having an address maintained by a write pointer and one or more output ports having addresses maintained by read pointers.

16. The integrated circuit of claim 14 wherein the reorder buffer further comprises multiple output ports coupled to different output voltage level shifters, the different output voltage shifters configured to provide the output data to different outputs of the plurality of outputs.

17. The integrated circuit of claim 7, wherein the output interface further comprises additional output distributed FIFO elements, wherein the output distributed FIFO element and the additional output distributed FIFO elements form an array of distributed FIFO elements, and wherein the routed data is striped across the array of distributed FIFO elements.

18. The integrated circuit of claim 7, wherein the input distributed FIFO element and the output distributed FIFO element each comprise a first segment and a second segment, wherein the first segment is physically located on one layer of a three-dimensional integrated circuit and the second segment is physically located on another layer of the three-dimensional integrated circuit, and wherein the first and second segments are coupled by vertical through-silicon via interconnects.

19. The integrated circuit of claim 18, wherein the first and second segments of the input and output distributed FIFO elements communicate differential signals.

20. The integrated circuit of claim 18, wherein the first and second segments of the input and output distributed FIFO elements communicate single ended signals.

21. A method comprising:

receiving data samples in a first sequential order, the data samples having a voltage level and a frequency;

selecting an output from a plurality of outputs, wherein the selected output has requirements for a voltage level and a frequency different from the received data samples;

routing the data samples to the selected output;

converting the voltage level of the data samples to an output voltage level compatible for the selected output;

converting the frequency of the data samples to an output frequency compatible for the selected output; and

reordering the data samples from a first sequential order to a second sequential order compatible for the selected output.

22. The method of claim 21, further comprising compressing the data samples based on run-length encoding, according to a requirement of the selected output.

23. The method of claim 21, further comprising encoding the data samples into one or more data strings, according to a requirement of the selected output.

24. The method of claim 21, further comprising encoding the data samples based on Gray code encoding, according to a requirement of the selected output.

25. The method of claim 21, wherein the converting the frequency of the data samples to an output frequency compatible for the selected output comprises adjusting a data rate of the data samples to a data rate compatible for the selected output.