Shared virtual memory between a host and discrete graphics device in a computing system

• US 8,451,281 B2
• Filed: 06/23/2009
• Issued: 05/28/2013
• Est. Priority Date: 06/23/2009
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ginzburg, Boris
• Primary Examiner(s): Crawford, Jacinta M
• Application Number:
  US12/489,954
• Publication Number:
  US 20100321397A1
• Time in Patent Office: 1,435 Days
• Field of Search: 345/501, 345/503, 345/530, 345/537, 345/541
• US Class Current: 345/541
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/455 Image or video data
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a device having a device processor and a device memory, the device to couple to a host having a host processor and a host memory, the host having a host page table to map first virtual addresses to physical addresses of the host memory, the device having a device page table to map second virtual addresses to physical addresses of the device memory, wherein on a page fault in the device, the device is to request a missing page from the host memory via the host page table and the host memory and the device memory appear to a user-level application as a single virtual memory space.

2. The apparatus of claim 1, wherein the device memory is to act as a page-based cache memory of the host memory.

3. The apparatus of claim 2, wherein coherency between the device memory and the host memory is maintained implicitly without programmer interaction.

4. The apparatus of claim 3, wherein a write protected page can be stored simultaneously in the host memory and the device memory.

5. The apparatus of claim 1, wherein the host is to provide the missing page from the host memory to the device if present therein, and to set a not present indicator in the host memory for the corresponding page if the missing page is write enabled, wherein when the not present indicator is set, the host is prevented from accessing the corresponding page in the host memory.

6. The apparatus of claim 1, wherein the host is to provide the missing page from a mass storage coupled to the host to the device if the missing page is not present in the host memory, wherein the host is to provide the missing page directly to the device from the mass storage without storage in the host memory.

7. The apparatus of claim 1, wherein the device and the host are formed on a single integrated circuit, the host processor comprises a general-purpose processor and the device processor comprises a graphics processor.

8. A method comprising:

receiving a page fault from a device processor of a device including the device processor and a device memory, the device coupled to a host including a host processor, a host memory, and a host page table that is to map a virtual address to a physical address of the host memory in response to a request initiated by the host processor, the device and the host asymmetrically sharing a virtual memory space;

sending a request from the device to the host for a page associated with the page fault; and

receiving the page by the device from the host, wherein the page is retrieved from storage by the host via the host page table, and wherein the page is locked in the host memory if the page is indicated to be write permissible.

9. The method of claim 8, further comprising allocating space in the device memory for the page before sending the request for the page to the host.

10. The method of claim 8, further comprising mapping the device memory using a device page table including a plurality of device entries, each device entry associating a corresponding virtual address to a corresponding physical address of the device memory, the virtual addresses symmetric to host virtual addresses of host entries of a host page table of the host, each host virtual address mapped to a corresponding physical address of the host memory.

11. The method of claim 10, further comprising maintaining coherency between the host memory and the device memory by indicating that a corresponding page of the host memory is inaccessible when the page is sent to the device and the page is writable.

12. The method of claim 8, further comprising using the host to handle the page fault occurring on the device, and not using the device to handle a page fault occurring on the host.

13. A system comprising:

a processor having a translation lookaside buffer (TLB) to store first virtual address to physical address translations for a memory;

the memory coupled to the processor to store a first plurality of pages each corresponding to one of the physical addresses;

a graphics processor coupled to the processor via an interconnect and including a graphics translation lookaside buffer (gTLB) to store second virtual address to physical address translations for a graphics memory; and

the graphics memory coupled to the graphics processor to store a second plurality of pages each corresponding to one of the physical addresses of the gTLB, wherein the TLB and the gTLB asymmetrically share virtual addresses of a single virtual address space;

wherein in response to a page fault associated with a first request to the graphics memory for a page, the graphics processor is to transmit a second request for the page to the processor and the processor is to provide the page to the graphics processor using the TLB.

14. The system of claim 13, wherein the graphics memory comprises a cache for the memory.

15. The system of claim 14, wherein the processor is to provide the page from the memory to the graphics memory via a direct memory access operation if the page is present in the memory.

16. The system of claim 13, wherein an application is to execute on the processor and the graphics processor using the single virtual address space.

17. The system of claim 16, wherein the application includes a first portion to operate on the processor using the memory and a second portion to operate on the graphics processor using the graphics memory.

18. The system of claim 13, wherein the processor is to obtain the page from a mass storage device coupled to the processor if the missing page is not present in the memory, wherein the processor is to provide the page directly from the mass storage device to the graphics memory without first storing the page in the memory.

19. The system of claim 13, wherein a write protected page can be simultaneously stored and accessed in the memory and the graphics memory, and a writable page can only be accessed in a single one of the memory and the graphics memory at a time.