Frame rate converter and display apparatus equipped therewith
First Claim
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1. A frame rate converter, comprising:
- an input unit configured to write, into a memory unit, frames successively input from the outside;
an interpolated frame generating unit configured to retrieve a plurality of original frames from the memory unit, generate an interpolated frame between the original frames, and write the interpolated frame into the memory unit; and
an output unit configured to retrieve original frames and an interpolated frame from the memory unit and output to the outside the frames in the order in which the frames are to be displayed, wherein;
the input unit, the interpolated frame generating unit, and the output unit operate in parallel to perform pipeline processing,operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit, andwithin the period between the termination of the input period of a target frame, in which the target frame is input to the input unit and written into the memory unit, and the initiation of the input period of the next frame, the interpolated frame generating unit completes the processing of retrieving at least the target frame, generating the interpolated frame with reference to at least the target frame, and writing the interpolated frame.
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Abstract
An input unit writes, into a memory unit, frames successively input from the outside. An interpolated frame generating unit reads multiple original frames from the memory unit, generates an interpolated frame between the original frames, and writes the interpolated frame into the memory unit. An output unit retrieves original frames and an interpolated frame from the memory unit and outputs to the outside the frames in the order in which the frames are to be displayed. The input unit, interpolated frame generating unit, and output unit operate in parallel to perform pipeline processing. Operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit.
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Citations
6 Claims
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1. A frame rate converter, comprising:
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an input unit configured to write, into a memory unit, frames successively input from the outside; an interpolated frame generating unit configured to retrieve a plurality of original frames from the memory unit, generate an interpolated frame between the original frames, and write the interpolated frame into the memory unit; and an output unit configured to retrieve original frames and an interpolated frame from the memory unit and output to the outside the frames in the order in which the frames are to be displayed, wherein; the input unit, the interpolated frame generating unit, and the output unit operate in parallel to perform pipeline processing, operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit, and within the period between the termination of the input period of a target frame, in which the target frame is input to the input unit and written into the memory unit, and the initiation of the input period of the next frame, the interpolated frame generating unit completes the processing of retrieving at least the target frame, generating the interpolated frame with reference to at least the target frame, and writing the interpolated frame. - View Dependent Claims (2, 3, 6)
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4. A frame rate converter, comprising:
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an input unit configured to write, into a memory unit, frames successively input from the outside; an interpolated frame generating unit configured to retrieve a plurality of original frames from the memory unit, generate an interpolated frame between the original frames, and write the interpolated frame into the memory unit; and an output unit configured to retrieve original frames and an interpolated frame from the memory unit and output to the outside the frames in the order in which the frames are to be displayed, wherein; the input unit, the interpolated frame generating unit, and the output unit operate in parallel to perform pipeline processing, operation timing of each of the input unit and the interpolated frame generating unit is determined so that the timing at which the input unit writes an original frame into the memory unit differs from the timing at which the interpolated frame generating unit writes an interpolated frame into the memory unit, and the number of frames to be input to the input unit is increased by duplication before the frames are input to the frame rate converter. - View Dependent Claims (5)
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Specification
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Current AssigneeSemiconductor Components Industries LLC (ON Semiconductor Corporation)
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Original AssigneeSanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
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InventorsFurukawa, Riichi, Otowa, Satoshi
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Primary Examiner(s)Natnael, Paulos M
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Application NumberUS12/847,613Publication NumberTime in Patent Office1,033 DaysField of Search348/441, 348/448, 348/452, 348/458, 348/459US Class Current348/441CPC Class CodesH04N 7/0132 the field or frame frequenc...
