Hybrid MRAM array structure and operation

• US 8,451,642 B2
• Filed: 04/05/2012
• Issued: 05/28/2013
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Seyyedy, Mirmajid, Hush, Glen
• Primary Examiner(s): DINH, SON T
• Application Number:
  US13/440,660
• Publication Number:
  US 20120188812A1
• Time in Patent Office: 418 Days
• Field of Search: 365/63, 365/230.03, 365/173
• US Class Current: 365/63
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Claims

1. A memory device comprising:

a first planar structure that includes at least one memory cell,

a first sense line, wherein the at least one memory cell is coupled to the first sense line and the first sense line is used to read the state of the memory cell;

a first sense interconnect line coupled to the first sense line; and

a second planar structure that includes a first access transistor coupled to the first sense interconnect line.

2. The memory device according to claim 1, wherein the at least one memory cell is an MRAM memory cell.

3. The memory device according to claim 1, further comprising a third planar structure including at least a second memory cell coupled to a second sense line, which is used to read the second memory cell, wherein the second sense line is coupled to the first sense interconnect line.

4. The memory device according to claim 1, wherein the first planar structure is formed above the second planar structure.

5. The memory device according to claim 1, wherein the first planar structure further includes a second memory cell coupled to the first sense line, which is used to read the state of the second memory cell.

6. The memory device according to claim 1, wherein the first planar structure further includes:

a second memory cell,

a second sense line, wherein the second memory cell is coupled to the second sense line and the second sense line is used to read the state of the second memory cell; and

a second sense interconnect line coupled to the second sense line; and

wherein the second planar structure further includes a second access transistor coupled to the second sense interconnect line.

7. The memory device according to claim 6, wherein the first and second access transistors are connected to a first sense amplifier.

8. The memory device according to claim 1, wherein at least one memory cell comprises:

a read/write common line;

a magnetic bit;

an insulating material, and

a write-only line, wherein the insulating material is formed between the first sense line and the write-only line.

9. The memory device according to claim 8, wherein the magnetic bit comprises a free ferromagnetic layer, a pinned ferromagnetic layer, and a tunnel junction layer formed between the free ferromagnetic layer and the pinned ferromagnetic layer.

10. A memory device comprising:

a first planar array of memory cells including a first memory cell;

a first sense line positioned along the first planar array of memory cells coupled to the first memory cell;

a second planar array of memory cells including a second memory cell;

a second sense line positioned along the second planar array of memory cells coupled to the second memory cell; and

a first sense interconnect line intersecting the first planar array and the second planar array, wherein the first sense line and the second sense line are coupled to the first interconnect line.

11. The memory device of claim 10, wherein the first sense line and the second sense line are configured to perform a reading function for their respective memory cells.

12. The memory device of claim 10, further comprising a third planar array of access devices including at least one access transistor coupled to the first sense interconnect line.

13. The memory device of claim 12, further comprising:

a third memory cell provided in the first planar array;

a third sense line positioned along the first planar array and coupled to the third memory cell;

a second interconnect line, wherein the third sense line is coupled to the second interconnect line; and

a second access transistor provided in the third planar array of access devices, wherein the second interconnect line is coupled to the second access transistor.

14. The memory device of claim 13, further comprising a sense amplifier coupled to the first access transistor and the second access transistor.

15. The memory device of claim 10, wherein the first planar array further comprises a write-only line positioned along the first planar array.

16. The memory device of claim 15, further comprising an insulating material, wherein the insulating material insulates the write-only line from the first sense line.

17. The memory device of claim 10, further comprising a read/write line in electrical communication with the first memory cell.

18. A memory device comprising:

a first planar structure including a first plurality of memory cells;

a first sense line, wherein a first set of the first plurality of memory cells is coupled to the first sense line and the first sense line is configured to read the first set of the first plurality of memory cells;

a second planar structure including a second plurality of memory cells;

a second sense line, wherein a second set of the second plurality of memory cells is coupled to the second sense line and the second sense line is configured to read the second set of the second plurality of memory cells; and

a first sense interconnect line, wherein the first sense line and the second sense line are coupled to the first sense interconnect line.

19. The memory device of claim 18, wherein each memory cell is coupled to a read/write line.

20. The memory device of claim 18, wherein each planar structure comprises a write-only line.

21. The memory device of claim 20, wherein the first planar structure further comprises an insulating material provided between the write-only line and the first sense line.

22. The memory device of claim 18, wherein the first sense interconnect line is coupled to a first access transistor.

23. The memory device of claim 22, wherein the first access transistor is provided in a third planar structure.

24. The memory device of claim 18, wherein each memory cell is a MRAM memory cell.

25. The memory device of claim 22, wherein the first access transistor is coupled to a sense amplifier.

26. The memory device of claim 25, further comprising:

a third sense line, wherein a third set of the first plurality of memory cells is coupled to the third sense line and the third sense line is configured to perform a read function of the third set of the first plurality of memory cells;

a fourth sense line, wherein a fourth set of the second plurality of memory cells is coupled to the fourth sense line and the fourth sense line is configured to perform a read function of the fourth set of the second plurality of memory cells;

a second sense interconnect line, wherein the third sense line and the fourth sense line are coupled to the second sense interconnect line; and

a second access transistor coupled to the second sense interconnect line and the sense amplifier.