Resistance control method for nonvolatile variable resistive element

• US 8,451,647 B2
• Filed: 06/10/2011
• Issued: 05/28/2013
• Est. Priority Date: 06/10/2010
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ishihara, Kazuya
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/157,620
• Publication Number:
  US 20110305070A1
• Time in Patent Office: 718 Days
• Field of Search: 365/100
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A resistance control method for a nonvolatile variable resistive element in a nonvolatile semiconductor memory device is provided. The device includes a memory cell array in which unit memory cells having nonvolatile variable resistive elements and transistors are arranged in a matrix. The memory cells that are targets of a memory operation are selected by first selection lines (word lines), second selection lines (bit lines) and third selection lines (source lines). The method includes steps of selecting one or more first selection lines, selecting a plurality of second selection lines, and applying a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation, such that the voltage necessary for the memory operation is applied to all of the selected memory cells.

Claims

1. A method of controlling a resistance of a nonvolatile variable resistive element, wherein

in a nonvolatile semiconductor memory device including a memory cell array in which a plurality of memory cells is arranged in row and column directions in a matrix, each memory cell being formed by connecting one terminal of the nonvolatile variable resistive element having two terminals in which electrodes are provided at both ends of a variable resistor, to one of other two terminals of a selection element, which has three terminals including a control terminal and the other two terminals that are other than the control terminal, the control terminal being for controlling an amount of current flowing across the other two terminals by current or voltage applied to the control terminal,

the nonvolatile variable resistive element is subjected to a forming process, so that its resistive state transitions between two or more different resistive states by applying an electrical stress across the both terminals of the nonvolatile variable resistive element, and one resistive state after the transition is used for storing information,

the each memory cell is configured such that

the control terminal of the selection element is connected to a first selection line, and

one of a terminal of the nonvolatile variable resistive element that is not connected to the selection element and a terminal of the selection element that is other than the control terminal and not connected to the nonvolatile variable resistive element is connected to a second selection line and the other thereof is connected to a third selection line,

the first selection line extends in the row direction and connects the memory cells belonging to the same row,

the second selection line extends in the column direction and connects the memory cells belonging to the same column, and

the memory cells in the memory array are mutually connected by the first selection line, the second selection line and the third selection line, and

the method comprises:

when one or more first selection lines and a plurality of second selection lines are to be selected, respectively and one of memory operations of a programming process, an erasure process, and the forming process is to be collectively performed on target memory cells that are all of the memory cells selected by the first selection lines and the second selection lines,

a first step of selecting the one or more of the first selection lines connected to the target memory cells to be subjected to the memory operation in the memory array and applying a predetermined selection voltage to all of the selected first selection lines;

a second step of selecting the plurality of second selection lines connected to the target memory cells in the memory array; and

a third step of applying, to each of the selected second selection lines, a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation of the nonvolatile variable resistive elements, the change in potential being dependent on a maximum number of the target memory cells that are commonly connected to each of the third selection lines to which the respective target memory cells on the selected second selection line are connected, such that the voltage that is necessary for the memory operation is applied to both terminals of all of the target memory cells.

2. The method of controlling a resistance of a nonvolatile variable resistive element according to claim 1, wherein

in the memory cell array, each of the third selection lines extends in the column direction, and the memory cells belonging to the same column are mutually connected by each of the third selection lines.

3. The method of controlling a resistance of a nonvolatile variable resistive element according to claim 1, wherein

the memory operation is the forming process.

4. The method of controlling a resistance of a nonvolatile variable resistive element according to claim 3, wherein

in the forming process, a bias condition for the selection elements in the memory cells is set such that the amount of current that flows in the nonvolatile variable resistive elements is equal to or lower than 50 μ

A.

5. The method of controlling a resistance of a nonvolatile variable resistive element according to claim 3, wherein

the nonvolatile semiconductor memory device is formed by connecting a forming detection circuit to the second selection line directly or via a decoder, or to the third selection line directly or via a decoder in a case where the third selection lines extend in the column direction, the forming detection circuit being for detecting, upon completion of the forming process, a change in current flowing through predetermined position in the second selection line or a change in potential at the predetermined position of the second selection line,

the method further comprising a fourth step in which, when the forming detection circuit detects the change in current or potential in a particular second selection line, the nonvolatile semiconductor memory device stops application of the voltage through the particular second selection line in a case where the forming process of all of the memory cells connected to the particular second selection line is completed.

6. The method of controlling a resistance of a nonvolatile variable resistive element according to claim 5, further comprising,

when the nonvolatile semiconductor memory device stops the application of the voltage through the particular second selection line in the fourth step,

a fifth step of setting the particular second selection line as unselected, recalculating the maximum number of the target memory cells to be subjected to the forming process that are commonly connected to each of the third selection lines to which the respective target memory cells on the respective selected second selection lines are connected, and applying, to each of the selected second selection lines, a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the forming process of the nonvolatile variable resistive elements.