Semiconductor device

• US 8,451,651 B2
• Filed: 02/15/2011
• Issued: 05/28/2013
• Est. Priority Date: 02/19/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori, Kato, Kiyoshi, Inoue, Hiroki, Nagatsuka, Shuhei
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): Yang, Han
• Application Number:
  US13/027,543
• Publication Number:
  US 20110205775A1
• Time in Patent Office: 833 Days
• Field of Search: 365/149, 365/185.08, 365/194, 365/230.06, 365/233.1
• US Class Current: 365/149
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device is formed using a material capable of sufficiently reducing the off-state current of a transistor, such as an oxide semiconductor material that is a widegap semiconductor. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor allows data to be held for a long time. In addition, the timing of potential change in a signal line is delayed relative to the timing of potential change in a write word line. This makes it possible to prevent a data writing error.

Claims

1. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a signal line;

a first memory cell;

a first driver circuit; and

a second driver circuit,

wherein the first memory cell comprises;

a first transistor comprising a first channel formation region;

a second transistor comprising a second channel formation region comprising an oxide semiconductor; and

a capacitor,

wherein a gate of the first transistor is electrically connected to one of two electrodes of the capacitor and one of a source and a drain of the second transistor,

wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor,

wherein the first driver circuit is electrically connected to one of a source and a drain of the first transistor through the bit line and electrically connected to the other of the source and the drain of the second transistor through the signal line,

wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to a gate of the second transistor through the write word line, and

wherein the second driver circuit is configured to delay a signal input to the signal line relative to a signal input to the write word line.

2. The semiconductor device according to claim 1, further comprising a potential conversion circuit configured to output a potential higher than a power supply potential to the second driver circuit.

3. The semiconductor device according to claim 1, further comprising a source line and a second memory cell wherein the first memory cell and the second memory cell are connected in series between the bit line and the source line.

4. The semiconductor device according to claim 1, further comprising:

a first switch configured to control a connection of the bit line and the signal line to an output terminal; and

a second switch configured to control a connection of the bit line and the signal line to an input terminal,

wherein the bit line and the signal line are electrically connected to each other.

5. The semiconductor device according to claim 1, wherein the first channel formation region comprises silicon.

6. The semiconductor device according to claim 2, wherein the second driver circuit comprises a level shift circuit electrically connected to the potential conversion circuit and the write word line or the read word line.

7. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a signal line;

a first memory cell;

a first driver circuit; and

a second driver circuit,

wherein the first memory cell comprises;

a first transistor comprising a first channel formation region;

a second transistor comprising a second channel formation region comprising an oxide semiconductor; and

a capacitor,

wherein a gate of the first transistor is electrically connected to one of two electrodes of the capacitor and one of a source and a drain of the second transistor,

wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor,

wherein the first driver circuit is electrically connected to one of a source and a drain of the first transistor through the bit line and electrically connected to the other of the source and the drain of the second transistor through the signal line,

wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to a gate of the second transistor through the write word line, and

wherein the first driver circuit comprises a delay circuit electrically connected to the signal line.

8. The semiconductor device according to claim 7, further comprising a potential conversion circuit configured to output a potential higher than a power supply potential to the second driver circuit.

9. The semiconductor device according to claim 7, further comprising a source line and a second memory cell wherein the first memory cell and the second memory cell are connected in series between the bit line and the source line.

10. The semiconductor device according to claim 7, further comprising:

a first switch configured to control a connection of the bit line and the signal line to an output terminal; and

a second switch configured to control a connection of the bit line and the signal line to an input terminal,

wherein the bit line and the signal line are electrically connected to each other.

11. The semiconductor device according to claim 7, wherein the first channel formation region comprises silicon.

12. The semiconductor device according to claim 8, wherein the second driver circuit comprises a level shift circuit electrically connected to the potential conversion circuit and the write word line or the read word line.

13. A semiconductor device comprising:

a write word line;

a read word line;

a bit line;

a signal line;

a first memory cell;

a first driver circuit comprising a first buffer circuit electrically connected to the signal line; and

a second driver circuit comprising a second buffer circuit electrically connected to the write word line,

wherein the first memory cell comprises;

a first transistor comprising a first channel formation region;

a second transistor comprising a second channel formation region comprising an oxide semiconductor; and

a capacitor,

wherein a gate of the first transistor is electrically connected to one of two electrodes of the capacitor and one of a source and a drain of the second transistor,

wherein the capacitor is configured to hold a voltage between the two electrodes of the capacitor by turning off the second transistor,

wherein the first driver circuit is electrically connected to one of a source and a drain of the first transistor through the bit line and electrically connected to the other of the source and the drain of the second transistor through the signal line,

wherein the second driver circuit is electrically connected to the other of the two electrodes of the capacitor through the read word line and electrically connected to a gate of the second transistor through the write word line, and

wherein a channel length of a transistor of the first buffer circuit is larger than a channel length of a transistor of the second buffer circuit.

14. The semiconductor device according to claim 13, further comprising a potential conversion circuit configured to output a potential higher than a power supply potential to the second driver circuit.

15. The semiconductor device according to claim 13, further comprising a source line and a second memory cell wherein the first memory cell and the second memory cell are connected in series between the bit line and the source line.

16. The semiconductor device according to claim 13, further comprising:

a first switch configured to control a connection of the bit line and the signal line to an output terminal; and

a second switch configured to control a connection of the bit line and the signal line to an input terminal,

wherein the bit line and the signal line are electrically connected to each other.

17. The semiconductor device according to claim 13, wherein the first channel formation region comprises silicon.

18. The semiconductor device according to claim 14, wherein the second driver circuit comprises a level shift circuit electrically connected to the potential conversion circuit and the write word line or the read word line.