System and method for recovery from memory errors in a medical device

• US 8,452,403 B2
• Filed: 10/25/2010
• Issued: 05/28/2013
• Est. Priority Date: 03/23/2004
• Status: Expired due to Fees

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Hoyme, Kenneth P., Larson, Aaron
• Primary Examiner(s): Koharski, Christopher D
• Assistant Examiner(s): MAHMOOD, NADIA AHMAD
• Application Number:
  US12/911,318
• Publication Number:
  US 20110040354A1
• Time in Patent Office: 946 Days
• Field of Search: 607/27, 607/59
• US Class Current: 607/27
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit

Abstract

A system comprising an implantable medical device that comprises a memory circuit, a radiation detector circuit configured to detect a condition correlative to a high-energy radiation level that exceeds a background radiation level, and a controller circuit. The control circuit checks memory locations for errors using a first rate of error checking per time period during a normal operation mode and, in response to the radiation detector circuit indicating a high-energy radiation level, initiates a memory scrubbing mode, wherein the memory scrubbing mode has an increased rate of error checking substantially all memory locations per time period in the memory circuit to check for any errors and correct any such errors.

Claims

1. A system comprising:

an implantable medical device, the implantable medical device comprising;

a memory circuit;

a radiation detector circuit configured to detect a condition correlative to a high-energy radiation level that exceeds a background radiation level; and

a controller circuit, communicatively coupled to the memory circuit and the radiation detector circuit, wherein the control circuit is configured to;

check memory locations for errors using a first rate of error checking per time period during a normal operation mode; and

,

in response to the radiation detector circuit indicating a high-energy radiation level, initiate a memory scrubbing mode, wherein the memory scrubbing mode has an increased rate of error checking substantially all memory locations per time period in the memory circuit and correcting detected errors, wherein the error checking and error correcting are performed more frequently when the radiation detector circuit indicates a high-energy radiation level is present than when the radiation detector circuit indicates that a high-energy radiation level is not present.

2. The system of claim 1, wherein the radiation detector circuit includes at least one memory cell of the memory circuit that is susceptible to lower levels of radiation energy than other memory cells of the memory circuit, and wherein the radiation detector circuit indicates a high radiation environment when having a rate of memory errors that exceeds a specified threshold memory error rate.

3. The system of claim 2, wherein the radiation detection circuit includes a plurality of memory cells susceptible to lower levels of radiation energy than other memory cells of the memory circuit, and

wherein the controller circuit is configured to detect, at a first checking rate, a rate of occurrence of errors in information stored in the memory circuit, and to compare the rate of occurrence of errors to a predetermined threshold, and to enter the memory scrubbing mode to increase the checking rate from the first checking rate value per time period to a second checking rate value per time period in response to the rate of occurrence of the errors exceeding the predetermined threshold.

4. The system of claim 1, wherein in response to the radiation detector circuit no longer indicating a high-energy radiation level, the controller circuit checks the memory circuit for any errors and corrects any such errors less frequently than when the radiation detector circuit indicates that a high-energy radiation level is present.

5. The system of claim 4, wherein the radiation detector circuit includes at least one memory cell of the memory circuit that is susceptible to lower levels of radiation energy than other memory cells of the memory circuit, and wherein the radiation detector circuit no longer indicates a high radiation environment when having a rate of memory errors less than a specified exit threshold memory error rate.

6. The system of claim 5, wherein the exit threshold memory error rate is equal to a memory scrubbing mode initiating threshold memory error rate.

7. The system of claim 1, wherein the radiation detector circuit includes the controller circuit and the memory circuit operating together to detect a rate of occurrence of errors in memory, wherein the controller is configured to compare a detected rate of occurrence of errors in memory in the memory circuit to a specified threshold value and to declare a high-energy radiation level if the detected rate exceeds the specified threshold value.

8. The system of claim 1, wherein in response to the radiation detector circuit indicating a high-energy radiation level, the controller circuit checks the memory circuit for any single bit errors in memory and corrects any such single bit errors.

9. The system of claim 1, wherein the implantable medical device includes:

at least one port to provide therapy to the patient; and

a therapy circuit coupled to the at least one port and the controller circuit, the therapy circuit operable to deliver therapy to the patient,

wherein the controller circuit is configured to withhold therapy when the implantable medical device enters the memory scrubbing mode.

20. The system of claim 1, wherein the controller circuit is configured to recurrently activate the radiation sensor circuit.

10. A method of operating an implantable medical device comprising:

checking memory locations for errors using a first rate of error checking per time period during a normal operation mode;

detecting a condition correlative to a high-energy radiation level that exceeds a background radiation level using a radiation detector circuit in the implantable medical device; and

initiating a memory scrubbing mode in the device, wherein the memory scrubbing mode includes an increased rate of error checking substantially all memory locations per time period to check for any errors and to correct any such errors, and

checking memory locations at a rate less than the increased rate of error checking per time period in response to no longer detecting the high-energy radiation level.

11. The method of claim 10, wherein detecting a condition correlative to a high-energy radiation level using the radiation detector circuit includes the implantable device detecting that one or more memory cells, that are susceptible to lower levels of radiation energy than other memory cells, have a rate of memory errors that exceeds a specified threshold memory error rate.

12. The method of claim 10, wherein detecting a condition correlative to a high-energy radiation level includes:

detecting, at a first checking rate, a rate of occurrence of errors in information stored in the memory locations, wherein the memory locations include a plurality of memory cells that are susceptible to lower levels of radiation energy than other memory cells of the memory, and

comparing the rate of occurrence of errors to a specified threshold memory error rate, and

wherein initiating the memory scrubbing mode includes entering the memory scrubbing mode to increase the checking rate from the first checking rate value per time period to a second checking rate value per time period in response to the rate of occurrence of the errors exceeding the specified threshold memory error rate.

13. The method of claim 10, wherein no longer detecting the high-energy radiation level includes detecting, in memory cells that include at least one memory cell of the memory circuit being susceptible to lower levels of radiation energy than other memory cells, a rate of memory errors less than a specified exit threshold memory error rate.

14. The method of claim 13, wherein the exit threshold memory error rate is equal to a threshold memory error rate that initiates the memory scrubbing mode.

15. The method of claim 10, wherein checking all memory locations per time period for any errors includes checking for any single bit errors in memory and correcting any such single bit errors.

16. The method of claim 10, including withholding a device-based therapy when the implantable medical device enters the memory scrubbing mode.

17. The method of claim 10, wherein initiating the memory scrubbing mode includes executing instructions implementing the memory scrubbing mode at a lower priority than instructions related to a device-based therapy.

19. The method of claim 10, wherein error checking and error correcting are performed more frequently when the radiation detector circuit indicates a high-energy radiation level is present than when the radiation detector circuit indicates that a high-energy radiation level is not present.

18. A system comprising:

an implantable medical device, the implantable medical device comprising;

a memory circuit;

means for determining a condition correlative to a high-energy radiation level that exceeds a background radiation level; and

a controller circuit, communicatively coupled to the memory circuit and the radiation detector circuit, wherein the control circuit is configured to;

check memory locations for errors using a first rate of error checking per time period during a normal operation mode; and

,

in response to the radiation detector circuit indicating a high-energy radiation level, initiate a memory scrubbing mode, wherein the memory scrubbing mode has an increased rate of error checking substantially all memory locations per time period in the memory circuit and correcting detected errors, wherein the error checking and error correcting are performed more frequently when the radiation detector circuit indicates a high-energy radiation level is present than when the radiation detector circuit indicates that a high-energy radiation level is not present.