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Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read

  • US 8,452,912 B2
  • Filed: 10/08/2009
  • Issued: 05/28/2013
  • Est. Priority Date: 10/11/2007
  • Status: Expired due to Fees
First Claim
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1. A smart-storage switch solid-state-drive (SSD) comprising:

  • a Non-Volatile Memory (NVM) that retains data when power is lost;

    a volatile memory that loses data when power is lost;

    a smart storage switch which comprises;

    a protocol converter, coupled to a host, for receiving host commands to access the NVM and for receiving host data and a host logical block address (LBA);

    a LBA range first-in-first-out (FIFO) having entries for storing the host LBA and a length of the host data;

    a volatile memory controller for interfacing to the volatile memory;

    a flash controller for interfacing to the NVM;

    a processor for controlling transfer of host data among the protocol converter, the LBA range FIFO, the volatile memory controller, and the flash controller;

    a sector data buffer, in the volatile memory, for storing the host data before writing to the NVM; and

    a lookup table, in the volatile memory, that maps pages in the host LBA to physical pages in a physical-block address (PBA) in the NVM;

    wherein the lookup table is page-mapped;

    wherein the processor operates to reduce writes to the NVM to reduce write acceleration;

    wherein the LBA range FIFO comprises sub-divided entries that are generated by the processor when a new host command has new host data that overlaps host data for a prior entry in the LBA range FIFO, the processor dividing the prior entry into a plurality of sub-divided entries in the LBA range FIFO;

    wherein sub-divided entries that are completely overlapped by new host data are invalidated and not written to the NVM;

    whereby writes to the NVM are reduced by invalidating overlapping sub-divided entries in the LBA range FIFO.

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