Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read
First Claim
1. A smart-storage switch solid-state-drive (SSD) comprising:
- a Non-Volatile Memory (NVM) that retains data when power is lost;
a volatile memory that loses data when power is lost;
a smart storage switch which comprises;
a protocol converter, coupled to a host, for receiving host commands to access the NVM and for receiving host data and a host logical block address (LBA);
a LBA range first-in-first-out (FIFO) having entries for storing the host LBA and a length of the host data;
a volatile memory controller for interfacing to the volatile memory;
a flash controller for interfacing to the NVM;
a processor for controlling transfer of host data among the protocol converter, the LBA range FIFO, the volatile memory controller, and the flash controller;
a sector data buffer, in the volatile memory, for storing the host data before writing to the NVM; and
a lookup table, in the volatile memory, that maps pages in the host LBA to physical pages in a physical-block address (PBA) in the NVM;
wherein the lookup table is page-mapped;
wherein the processor operates to reduce writes to the NVM to reduce write acceleration;
wherein the LBA range FIFO comprises sub-divided entries that are generated by the processor when a new host command has new host data that overlaps host data for a prior entry in the LBA range FIFO, the processor dividing the prior entry into a plurality of sub-divided entries in the LBA range FIFO;
wherein sub-divided entries that are completely overlapped by new host data are invalidated and not written to the NVM;
whereby writes to the NVM are reduced by invalidating overlapping sub-divided entries in the LBA range FIFO.
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Accused Products
Abstract
A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC'"'"'s for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
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Citations
21 Claims
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1. A smart-storage switch solid-state-drive (SSD) comprising:
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a Non-Volatile Memory (NVM) that retains data when power is lost; a volatile memory that loses data when power is lost; a smart storage switch which comprises; a protocol converter, coupled to a host, for receiving host commands to access the NVM and for receiving host data and a host logical block address (LBA); a LBA range first-in-first-out (FIFO) having entries for storing the host LBA and a length of the host data; a volatile memory controller for interfacing to the volatile memory; a flash controller for interfacing to the NVM; a processor for controlling transfer of host data among the protocol converter, the LBA range FIFO, the volatile memory controller, and the flash controller; a sector data buffer, in the volatile memory, for storing the host data before writing to the NVM; and a lookup table, in the volatile memory, that maps pages in the host LBA to physical pages in a physical-block address (PBA) in the NVM; wherein the lookup table is page-mapped; wherein the processor operates to reduce writes to the NVM to reduce write acceleration; wherein the LBA range FIFO comprises sub-divided entries that are generated by the processor when a new host command has new host data that overlaps host data for a prior entry in the LBA range FIFO, the processor dividing the prior entry into a plurality of sub-divided entries in the LBA range FIFO; wherein sub-divided entries that are completely overlapped by new host data are invalidated and not written to the NVM; whereby writes to the NVM are reduced by invalidating overlapping sub-divided entries in the LBA range FIFO. - View Dependent Claims (2, 3, 4)
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5. A smart-storage switch solid-state-drive (SSD) comprising:
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a Non-Volatile Memory (NVM) that retains data when power is lost; a volatile memory that loses data when power is lost; a smart storage switch which comprises; a protocol converter, coupled to a host, for receiving host commands to access the NVM and for receiving host data and a host logical block address (LBA); a LBA range first-in-first-out (FIFO) having entries for storing the host LBA and a length of the host data; a volatile memory controller for interfacing to the volatile memory; a flash controller for interfacing to the NVM; a processor for controlling transfer of host data among the protocol converter, the LBA range FIFO, the volatile memory controller, and the flash controller; a sector data buffer, in the volatile memory, for storing the host data before writing to the NVM; and a lookup table, in the volatile memory, that maps pages in the host LBA to physical pages in a physical-block address (PBA) in the NVM; wherein the lookup table is page-mapped; wherein the processor operates to reduce writes to the NVM to reduce write acceleration; wherein the protocol converter further receives a host cyclical-redundancy-check (CRC) from the host; further comprising; a CRC generator that receives the host data from the protocol converter and generates a generated CRC from the host data; wherein the protocol converter discards the host data when the host CRC mismatches the generated CRC; wherein the host CRC or the generated CRC is stored in the volatile memory as a stored CRC; wherein when the host LBA matches a cached LBA for a matching entry in the volatile memory, the stored CRC is read from the volatile memory and compared to the host CRC or generated CRC to signal a CRC match; when the CRC match is signaled, comparing all bytes in the host data to stored bytes for the matching entry in the volatile memory and signaling a data match when all byte match; when the data match is signaled, discarding the host data and not writing the host data to the volatile memory, whereby writing duplicate host data to the NVM is avoided by comparison of the stored CRC. - View Dependent Claims (6, 7)
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8. A smart-storage switch solid-state-drive (SSD) comprising:
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a Non-Volatile Memory (NVM) that retains data when power is lost; a volatile memory that loses data when power is lost; a smart storage switch which comprises; a protocol converter, coupled to a host, for receiving host commands to access the NVM and for receiving host data and a host logical block address (LBA); a LBA range first-in-first-out (FIFO) having entries for storing the host LBA and a length of the host data; a volatile memory controller for interfacing to the volatile memory; a flash controller for interfacing to the NVM; a processor for controlling transfer of host data among the protocol converter, the LBA range FIFO, the volatile memory controller, and the flash controller; a sector data buffer, in the volatile memory, for storing the host data before writing to the NVM; and a lookup table, in the volatile memory, that maps pages in the host LBA to physical pages in a physical-block address (PBA) in the NVM; wherein the lookup table is page-mapped; wherein the processor operates to reduce writes to the NVM to reduce write acceleration; a pattern detector for comparing an initial byte of the host data to subsequent bytes of the host data and signaling a pattern match when the initial byte is repeated for the subsequent bytes; a meta-data code generator for generating a meta-data code from the initial byte when the pattern detector signals the pattern match; and a meta-data mapping table storing meta-pointer entries; wherein the processor loads an entry in the lookup table with a pointer to a meta-pointer entry in the meta-data mapping table when the pattern match is signaled; wherein the meta-pointer entry identifies a meta entry in a meta-pattern block, the meta entry containing the meta-data code generated by the meta-data code generator. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A computer-implemented method for reducing writes to flash memory in a flash-memory system comprising:
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receiving host data for a host write command and storing the host data in a sector data cache at a location identified by a buffer pointer; receiving the host write command from a host and loading a starting logical block address (LBA), a length of the host transfer in sectors, and the buffer pointer into a current entry in a LBA range FIFO; detecting a range overlap of the current entry with a prior entry in the LBA range FIFO; sub-dividing the prior entry into sub-divided entries in the LBA range FIFO when the range overlap is detected by dividing the prior entry at the starting LBA and at an end that is the starting LBA plus the length of the current entry; invalidating a sub-divided entry that is completely overlapped by the current entry in the LBA range FIFO; delaying writing the host data from the sector data cache to a flash memory until after a host read command is received from the host; wherein the host tread command triggers writing to the flash memory. - View Dependent Claims (18)
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19. A solid-state-drive (SSD) comprising:
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Non-Volatile Memory (NVM) means for storing data that is retained when power is lost; volatile memory means for storing data that is lost when power is lost; a smart storage switch which comprises; protocol converter means, coupled to a host, for receiving host commands to access the NVM means and for receiving host data and a host logical block address (LBA); a LBA range first-in-first-out (FIFO) having entries for storing the host LBA and a length of the host data; volatile memory controller means for interfacing to the volatile memory means; flash controller means for interfacing to the NVM means; processor means for controlling transfer of host data among the protocol converter means, the LBA range FIFO, the volatile memory controller means, and the flash controller means; sector data buffer means, in the volatile memory means, for storing the host data before writing to the NVM means; and lookup table means, in the volatile memory means, for mapping pages in the host LBA to physical pages in a physical-block address (PBA) in the NVM means; wherein the lookup table means is page-mapped; wherein the LBA range FIFO comprises sub-divided entries that are generated by the processor means when a new host command has new host data that overlaps host data for a prior entry in the LBA range FIFO, the processor means further for dividing the prior entry into a plurality of sub-divided entries in the LBA range FIFO; wherein sub-divided entries that are completely overlapped by new host data are invalidated and not written to the NVM means; wherein the processor means is further for delaying writing the host data for entries in the LBA range FIFO into the NVM means until a host read is received by the protocol converter means, wherein the processor means operates to reduce writes to the NVM means to reduce write acceleration. - View Dependent Claims (20, 21)
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Specification