Solid state storage device controller with expansion mode

• US 8,452,916 B2
• Filed: 05/29/2012
• Issued: 05/28/2013
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Klein, Dean
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/482,517
• Publication Number:
  US 20120233392A1
• Time in Patent Office: 364 Days
• Field of Search: 711/2, 711/103, 711/154
• US Class Current: 711/103
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Claims

1. A solid state storage device controller comprising:

a memory control circuit for controlling at least a primary, faster memory device in a non-expansion memory mode and the primary memory device and an expansion, faster memory device in an expansion mode; and

a plurality of memory communication channels configured to couple slower memory devices to the solid state storage device controller wherein, in the expansion mode, at least one of the plurality of memory communication channels is configured to couple the expansion, faster memory device to the memory control circuit,

wherein a time to access the faster memory devices is less than a time to access the slower memory devices;

further wherein the memory control circuit is a plurality of sequencers configured to control the timing and control signals to the primary memory in the non-expansion memory mode and controls the timing and control signals to both the primary and the expansion memory devices in the expansion mode.

2. The solid state storage device controller of claim 1 and further including a host interface for communicating with an external device.

3. The solid state storage device controller of claim 2 wherein the external device is a computer.

4. The solid state storage device controller of claim 1 wherein at least some of the communication channels are coupled to a group of non-volatile memory devices that are each a different subset of the plurality of slower memory devices.

5. The solid state storage device controller of claim 1 and further including a CPU for controlling operation of the solid state storage device controller.

6. The solid state storage device controller of claim 1 wherein, in the non-expansion memory mode, the plurality of memory communication channels are configured to be coupled only to the at least one slower memory device.

7. The solid state storage device controller of claim 1 wherein each memory communication channel is comprised of address, data, and control signals.

8. The solid state storage device controller of claim 1 wherein each of the at least one slower memory devices are NAND architecture flash memory devices.

9. A solid state storage device controller comprising:

a memory control circuit comprising a plurality of sequencers that are configured to control a primary volatile memory device in a non-expansion memory mode and the primary volatile memory device and an expansion volatile memory device in an expansion mode; and

a plurality of non-volatile memory communication channels configured to couple a plurality of slower, non-volatile memory devices, relative to the primary volatile memory device, to the solid state storage device controller wherein, in the expansion mode, at least one of the plurality of non-volatile memory communication channels couples the expansion volatile memory device to the memory control circuit,

wherein the primary volatile memory device and the expansion volatile memory device have a substantially same access time.

10. The solid state storage device controller of claim 9 wherein the plurality of sequencers comprise a primary DRAM sequencer configured to generate timing and commands for the primary memory device.

11. The solid state storage device controller of claim 10 wherein the plurality of sequencers further comprise a secondary DRAM sequencer configured to generate timing and commands for the expansion memory device.

12. The solid state storage device controller of claim 10 wherein the plurality of sequencers further comprise a plurality of non-volatile memory sequencers configured to generate timing and commands for non-volatile memory devices coupled to the plurality of communication channels.

13. The solid state storage device controller of claim 10 wherein the primary memory device and the expansion memory device are DRAM.

14. A solid state storage device controller comprising:

a memory control circuit comprising a plurality of sequencers that are configured to control a primary DRAM and a plurality of non-volatile memory devices in a non-expansion memory mode and the primary DRAM, an expansion DRAM, and the plurality of non-volatile memory devices in an expansion mode; and

a plurality of non-volatile memory communication channels configured to couple the plurality of non-volatile memory devices to the solid state storage device controller wherein, in the expansion mode, a pair of the plurality of non-volatile memory communication channels couples the expansion DRAM to the memory control circuit.

15. The solid state storage device controller of claim 14 and further comprising a multiplexer coupled between the plurality of sequencers and the plurality of communication channels.

16. The solid state storage device controller of claim 14 wherein the pair of the plurality of memory communication channels comprise a data bus and an address bus in the expansion mode.

17. The solid state storage device controller of claim 14 and further comprising a host interface configured to couple the solid state storage device controller to a host device.

18. The solid state storage device controller of claim 17 wherein the host interface comprises one of parallel ATA, SATA, SAS, PCIe, fiber channel, SCSI, or Gigabit Ethernet.

19. The solid state storage device controller of claim 14 wherein the primary DRAM is coupled to and controlled by a primary DRAM sequencer of the plurality of sequencers and the expansion DRAM is coupled to and controlled by a secondary DRAM sequencer of the plurality of sequencers wherein the primary and secondary DRAM sequencers comprise the same function.