Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
First Claim
1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:
- examining, by a hardware wake-and-go engine, an instruction stream being pre-fetched for a thread to detect a programming idiom that indicates the thread will be waiting for an event that modifies a data value at a target address, wherein the hardware wake-and-go engine comprises hardware logic associated with a bus and a content addressable memory and wherein examining the instruction stream is performed prior to execution of the instruction stream;
in response to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, storing an entry in the content addressable memory with the target address;
responsive to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, storing thread state information for the thread and placing the thread in a sleep state;
snooping, by the hardware wake-and-go engine, the bus;
responsive to the hardware wake-and-go engine detecting a transaction on the bus associated with the target address, determining whether the transaction corresponds to the event that modifies the data value at the target address; and
responsive to determining the transaction corresponds to the event that modifies the target address, placing the thread in a non-sleep state.
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Accused Products
Abstract
A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom. When the thread reaches a programming idiom, the thread goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an event at the target addresses, and may wake the one or more threads waiting for the event.
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Citations
17 Claims
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1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:
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examining, by a hardware wake-and-go engine, an instruction stream being pre-fetched for a thread to detect a programming idiom that indicates the thread will be waiting for an event that modifies a data value at a target address, wherein the hardware wake-and-go engine comprises hardware logic associated with a bus and a content addressable memory and wherein examining the instruction stream is performed prior to execution of the instruction stream; in response to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, storing an entry in the content addressable memory with the target address; responsive to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, storing thread state information for the thread and placing the thread in a sleep state; snooping, by the hardware wake-and-go engine, the bus; responsive to the hardware wake-and-go engine detecting a transaction on the bus associated with the target address, determining whether the transaction corresponds to the event that modifies the data value at the target address; and responsive to determining the transaction corresponds to the event that modifies the target address, placing the thread in a non-sleep state. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing system, comprising:
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a processor; a bus; a hardware wake-and-go engine that comprises hardware logic associated with the bus; and a content addressable memory associated with the hardware wake-and-go engine, wherein the hardware wake-and-go engine is configured to; examine an instruction stream being pre-fetched for a thread running on the processor to detect a programming idiom that indicates the thread will be waiting for an event that modifies a data value at a target address, wherein examining the instruction stream is performed prior to execution of the instruction stream; in response to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, store an entry in the content addressable memory with the target address; responsive to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, store thread state information for the thread and place the thread in a sleep state; snoop the bus for a transaction associated with the target address; responsive to the hardware wake-and-go engine detecting the transaction On the bus associated with the target address, determine whether the transaction corresponds to the event that modifies the data value at the target address; and responsive to determining the transaction correspond to the event that modifies the target address, place the thread in a non-sleep state. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A hardware wake-and-go engine, comprising:
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hardware logic associated with a bus; and a content addressable memory, wherein the hardware wake-and-go engine is configured to; examine an instruction stream being pre-fetched for a thread to detect a programming idiom that indicates the thread will be waiting for an event that modifies a data value at a target address, wherein examining the instruction stream is performed prior to execution of the instruction stream; in response to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, store an entry in the content addressable memory with the target address; responsive to the hardware wake-and-go engine detecting the programming idiom in the instruction stream, store thread state information for the thread and place the thread in a sleep state; snoop the bus for a transaction associated with the target address; responsive to the hardware wake-and-go engine detecting the transaction on the bus associated with the target address, determine whether the transaction corresponds to the event that modifies the data value at the target address; and responsive to determining the transaction corresponds to the event that modifies the target address, place the thread in a non-sleep state. - View Dependent Claims (16, 17)
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Specification