Automated lithographic hot spot detection employing unsupervised topological image categorization
First Claim
1. A method of modifying lithographic hot spots in a chip design layout comprising:
- generating a set of reference feature key points by performing, employing at least one computing means, a first scale invariant feature transformation (SIFT) on a reference pattern including a lithographic hot spot located in a first chip design layout;
generating a set of target feature key points by performing, employing said at least one computing means, a second SIFT on a target pattern located in a second chip design layout;
matching said set of reference feature key points with said set of target feature key points by identifying, employing said at least one computing means, pairs of feature key points across said set of reference feature key points and said set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said set of target feature key points; and
storing data representing a result of said matching in a non-transitory machine readable data storage medium employing said at least one computing means, wherein said stored data represents presence of at least one lithographic hot spot in said target pattern;
modifying said stored data to enhance printability of said chip design layout employing said at least one computing means.
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Abstract
A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout.
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Citations
20 Claims
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1. A method of modifying lithographic hot spots in a chip design layout comprising:
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generating a set of reference feature key points by performing, employing at least one computing means, a first scale invariant feature transformation (SIFT) on a reference pattern including a lithographic hot spot located in a first chip design layout; generating a set of target feature key points by performing, employing said at least one computing means, a second SIFT on a target pattern located in a second chip design layout; matching said set of reference feature key points with said set of target feature key points by identifying, employing said at least one computing means, pairs of feature key points across said set of reference feature key points and said set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said set of target feature key points; and storing data representing a result of said matching in a non-transitory machine readable data storage medium employing said at least one computing means, wherein said stored data represents presence of at least one lithographic hot spot in said target pattern; modifying said stored data to enhance printability of said chip design layout employing said at least one computing means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system for modifying lithographic hot spots in a chip design layout, said system comprising at least one computing means including a processor, wherein said at least one computing means is configured to perform the steps of:
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generating a set of reference feature key points by performing a first scale invariant feature transformation (SIFT) on a reference pattern including a lithographic hot spot and located in a first chip design layout; generating a set of target feature key points by performing a second SIFT on a target pattern located in a second chip design layout; matching said set of reference feature key points with said set of target feature key points by identifying pairs of feature key points across said set of reference feature key points and said set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said set of target feature key points; storing data representing a result of said matching in a non-transitory machine readable data storage medium, wherein said stored data represents presence of at least one lithographic hot spot in said target pattern; and modifying said stored data to enhance printability of said chip design layout. - View Dependent Claims (17, 18, 19, 20)
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Specification