Automated lithographic hot spot detection employing unsupervised topological image categorization

• US 8,453,075 B2
• Filed: 09/02/2011
• Issued: 05/28/2013
• Est. Priority Date: 09/02/2011
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Wei, Leslie, Alan J.
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US13/224,402
• Publication Number:
  US 20130061184A1
• Time in Patent Office: 634 Days
• Field of Search: None
• US Class Current: 716/52
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout.

Claims

1. A method of modifying lithographic hot spots in a chip design layout comprising:

generating a set of reference feature key points by performing, employing at least one computing means, a first scale invariant feature transformation (SIFT) on a reference pattern including a lithographic hot spot located in a first chip design layout;

generating a set of target feature key points by performing, employing said at least one computing means, a second SIFT on a target pattern located in a second chip design layout;

matching said set of reference feature key points with said set of target feature key points by identifying, employing said at least one computing means, pairs of feature key points across said set of reference feature key points and said set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said set of target feature key points; and

storing data representing a result of said matching in a non-transitory machine readable data storage medium employing said at least one computing means, wherein said stored data represents presence of at least one lithographic hot spot in said target pattern;

modifying said stored data to enhance printability of said chip design layout employing said at least one computing means.

2. The method of claim 1, further comprising determining whether a total number of matches between said set of reference feature key points and said set of target feature key points is greater than a predetermined number.

3. The method of claim 1, further comprising identifying a region in said target pattern that generates a greater areal density of matches during said matching than the rest of said target pattern.

4. The method of claim 3, further comprising:

generating, employing said at least one computing means, at least one sub-target pattern having a total area less than a total area of said target pattern and including said region; and

generating at least another set of target feature key points by performing, employing said at least one computing means, an additional SIFT on each of said at least one sub-target pattern.

5. The method of claim 4, further comprising matching said set of reference feature key points with said at least another set of target feature key points by identifying, employing said at least one computing means, pairs of feature key points across said set of reference feature key points and said at least another set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said at least another set of target feature key points.

6. The method of claim 4, wherein a first sub-target pattern is generated by reducing an area of said target pattern, and each of said at least one sub-target pattern other than said first sub-target pattern is generated iteratively by successively reducing an area of an immediately preceding sub-target pattern.

7. The method of claim 1, wherein said set of reference feature key points is generated by:

generating a reference difference of Gaussian (DoG) function from said reference pattern; and

locating extrema of said reference DoG function as a function of two-dimensional coordinates in said reference function,

and said set of target feature key points is generated by;

generating a target DoG function from said target pattern; and

locating extrema of said target DoG function as a function of two-dimensional coordinates in said target function.

8. The method of claim 7, wherein said extrema of said reference DoG function are determined for a first fixed value of a sigma parameter for said reference DoG function, and said extrema of said target DoG function are determined for a second fixed value of a sigma parameter for said target DoG function, wherein said first fixed value and said second fixed value do not deviate from a ratio of a minimum dimension in said reference pattern to a minimum dimension in said target pattern by more than 20%.

9. The method of claim 8, further comprising:

generating a reference image orientation function and a reference gradient magnitude function from said reference pattern; and

generating a target image orientation function and a target gradient magnitude function from said target pattern,

wherein said topological features of said set of reference feature key points are characterized by a set of first three component vectors including a value of said reference DoG function, a value of said reference image orientation function, and a value of said reference gradient magnitude function at each of said reference feature key point in said set of reference feature key points, and said topological features of said set of target feature key points are characterized by a set of second three component vectors including a value of said target DoG function, a value of said target image orientation function, and a value of said target gradient magnitude function at each of said target feature key point in said set of target feature key points.

10. The method of claim 9, wherein said pairs are selected to minimize a Euclidean distance between a corresponding first three component vector and a corresponding second three component vector among all possible combinations of a previously unmatched first three component vector and a previously unmatched second three component vector.

11. The method of claim 1, further comprising adding at least one marker layer to said second chip design layout, wherein each of said at least one marker layer represents locations of said at least one lithographic hot spot in said target pattern in said second chip design layout.

12. The method of claim 11, further comprising running, employing said at least one computing means, a program that automatically corrects features in said at least one lithographic hot spot based on a pre-programmed algorithm.

13. The method of claim 1, wherein said data is stored in a form of a netlist or in a data format used for the exchange of layout data of integrated circuits.

14. The method of claim 1, wherein said reference pattern and said target pattern represent a set of line structures configured to provide lateral electrically conductive paths in a semiconductor chip.

15. The method of claim 1, wherein said reference pattern and said target pattern represent a set of contact via structures configured to provide vertical electrically conductive paths in a semiconductor chip.

16. A system for modifying lithographic hot spots in a chip design layout, said system comprising at least one computing means including a processor, wherein said at least one computing means is configured to perform the steps of:

generating a set of reference feature key points by performing a first scale invariant feature transformation (SIFT) on a reference pattern including a lithographic hot spot and located in a first chip design layout;

generating a set of target feature key points by performing a second SIFT on a target pattern located in a second chip design layout;

matching said set of reference feature key points with said set of target feature key points by identifying pairs of feature key points across said set of reference feature key points and said set of target feature key points, wherein each of said pairs are selected to provide maximum matching between topological features of said set of reference feature key points and topological features of said set of target feature key points;

storing data representing a result of said matching in a non-transitory machine readable data storage medium, wherein said stored data represents presence of at least one lithographic hot spot in said target pattern; and

modifying said stored data to enhance printability of said chip design layout.

17. The system of claim 16, wherein said at least one computing means is configured to perform a further step of determining whether a total number of matches between said set of reference feature key points and said set of target feature key points is greater than a predetermined number.

18. The system of claim 16, wherein said at least one computing means is configured to perform a further step of identifying a region in said target pattern that generates a greater areal density of matches during said matching than the rest of said target pattern.

19. The system of claim 18, wherein said at least one computing means is configured to perform the further steps of:

generating, employing said at least one computing means, at least one sub-target pattern less than said target pattern and including said region; and

generating at least another set of target feature key points by performing, employing said at least one computing means, an additional SIFT on each of said at least one sub-target pattern.

20. The system of claim 16, wherein said set of reference feature key points is generated by:

generating a reference difference of Gaussian (DoG) function from said reference pattern; and

locating extrema of said reference DoG function as a function of two-dimensional coordinates in said reference function,

and said set of target feature key points is generated by;

generating a target DoG function from said target pattern; and

locating extrema of said target DoG function as a function of two-dimensional coordinates in said target function.