System and method for analyzing power consumption of electronic design undergoing emulation or hardware based simulation acceleration

• US 8,453,086 B2
• Filed: 06/05/2006
• Issued: 05/28/2013
• Est. Priority Date: 06/03/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Tung, Tung-Sun, Lin, Tsair-Chin, Zhu, Bing
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US11/422,314
• Publication Number:
  US 20060277509A1
• Time in Patent Office: 2,549 Days
• Field of Search: 716 4- 6, 716/16, 716/17, 716/109, 716/133, 702/108, 703/23, 703/15
• US Class Current: 716/109
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of “events” which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.

Claims

1. A method for calculating power consumption of a logic design by using a computer or a processor, the method comprising:

programming the logic design into a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

emulating the logic design in the hardware logic emulation system;

running application software on the logic design being emulated in the hardware logic emulation system during a first sample period, wherein the first sample period comprises a first predetermined number of clock cycles;

collecting a number of state transitions between logic level high and logic level low and duty cycle for each logic gate and register in the logic design for state transitions taking place during the first sample period;

producing transition activity data using the collected number of state transitions and the duty cycle;

feeding design hierarchy information of the logic design to a power calculation software tool running in the computer or processor;

feeding the transition activity data to the power calculation software tool; and

calculating static and dynamic power consumed by at least a portion of the logic design using the design hierarchy information and the number of state transitions and the duty cycle for each of the logic gates and the registers in the logic design that was collected during said first sample period, wherein the static and dynamic power is calculated by the power calculation software tool; and

changing the logic design to optimize power consumption.

2. The method of claim 1 further comprising:

running the application software on the logic design being emulated in the hardware logic emulation system during a second sample period, the second sample period comprising a first predetermined number of clock cycles;

collecting a number of state transitions between logic level high and logic level low and duty cycle for each logic gate and register in the logic design for state transitions taking place during the second sample period;

calculating static and dynamic power consumed by at least the portion of the logic design using the number of state transitions and the duty cycle collected during said second sample period; and

plotting power consumption calculated for said first sample period and said second sample period on a graph, thereby displaying the static and dynamic power consumed by the emulated logic design.

3. The method of claim 1 wherein each of the plurality of integrated circuits comprise a programmable logic device.

4. The method of claim 1 wherein each of the plurality of integrated circuits comprise a processor chip.

5. The method of claim 1 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

6. A method for calculating power consumption of a logic design by using a computer or a processor, the method comprising:

programming the logic design into a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

defining a power event, said power event defined by a triggering condition comprising predetermined logic states for specified nodes in the logic design;

defining a sampling window, said sampling window comprising a plurality of segments, each of said segments defining how many cycles of a clock driving the logic design for which circuit transition data for each logic gate and register in the logic design will be collected;

emulating the logic design in the hardware logic emulation system;

running application software on the logic design being emulated in the hardware logic emulation system during the plurality of segments;

when said power event occurs during the emulation of the logic design, collecting state transition activity data wherein the state transition activity data comprises a number of state transitions and duty cycle for each logic gate and register in the logic design during each of said plurality of segments, wherein state transitions comprise transitions between logic level high and logic level low;

feeding design hierarchy information of the logic design to a power calculation software tool running in the computer or processor;

feeding the transition activity data to the power calculation software tool;

calculating static and dynamic power consumed by at least a portion of the logic design using the design hierarchy information, the state transition activity data and the duty cycle collected during each of said plurality of segments, wherein the static and dynamic power is calculated by the power calculation software tool; and

plotting static and dynamic power consumption calculated for each of said plurality of segments on a graph, thereby displaying power consumed by the logic design; and

changing the logic design to optimize power consumption.

7. The method of claim 6 wherein each of the plurality of integrated circuits comprise a programmable logic device.

8. The method of claim 6 wherein each of the plurality of integrated circuits comprise a processor chip.

9. The method of claim 6 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

10. A method for calculating power consumption of a logic design by using a computer or a processor, the method comprising:

programming the logic design into a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

emulating the logic design in said hardware logic emulation system;

running application software on the logic design being emulated in the hardware logic emulation system during a power evaluation period;

collecting state transition activity data for each logic gate and register in the logic design while the logic design is emulated over the power evaluation period, wherein the state transition activity data comprises a number of state transitions and duty cycle for each logic gate and register in the logic design during the power evaluation period, and wherein state transitions comprise transitions between logic level high and logic level low;

dividing said power evaluation period into a plurality of windows, wherein each of said plurality of windows is defined by a predetermined number of segments, each of said segments comprising state transition activity data for a number of clock cycles taking place during a time period while the logic design was run in said hardware logic emulation system;

feeding design hierarchy information of the logic design to a power calculation software tool running in the computer or processor;

feeding the transition activity data to the power calculation software tool;

calculating static and dynamic power consumed by at least a portion of the logic design using the design hierarchy information and the state transition activity data and the duty cycle for each of said segments, wherein the static and dynamic power is calculated by the power calculation software tool;

plotting static and dynamic power consumption calculated for each of said plurality of segments on a graph, thereby displaying power consumed by the logic design; and

changing the logic design to optimize power consumption.

11. The method of claim 10 wherein during periods of low power consumption, said windows have fewer segments than during periods of higher power consumption.

12. The method of claim 10 wherein during periods of high power consumption, said windows have more segments than during periods of low power consumption.

13. The method of claim 10 wherein said windows are comprised of segments that collect the transition activity data for a smaller number of clock cycles so a user can see power consumption for a smaller period of time at higher resolution.

14. The method of claim 10 wherein each of the plurality of integrated circuits comprise a programmable logic device.

15. The method of claim 10 wherein each of the plurality of integrated circuits comprise a processor chip.

16. The method of claim 10 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

17. A method for calculating power consumption of a logic design by using a computer or a processor, the method comprising:

programming the logic design into a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

emulating the logic design in said hardware logic emulation system;

running application software on the logic design being emulated in the hardware logic emulation system during a sample period;

identifying a predetermined operation of the logic design, the predetermined operation having a higher power consumption probability;

providing an adjustable time scale that defines a number of cycles of a clock driving the logic design for which state transition activity data for each logic gate and register in the logic design will be collected during the sample period, the state transition activity data comprising a number of state transitions and duty cycle for each logic gate and register in the logic design during the sample period, where state transitions comprise transitions between logic level high and logic level low, the number of the clock cycles driving the logic design during the predetermined operation being greater than the number of the clock cycles driving the logic design during other logic circuit operations;

collecting said state transition activity data in accordance with the adjustable time scale;

feeding design hierarchy information of the logic design to a power calculation software tool running in the computer or processor;

feeding the state transition activity data to the power calculation software tool; and

calculating static and dynamic power consumed by at least a portion of the logic design using the design hierarchy information and the state transition activity data and the duty cycle collected during the sample period,

wherein the static and dynamic power is calculated by the power calculation software tool; and

changing the logic design to optimize power consumption.

18. The method of claim 17 wherein each of the plurality of integrated circuits comprise a programmable logic device.

19. The method of claim 17 wherein each of the plurality of integrated circuits comprise a processor chip.

20. The method of claim 17 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

21. A method for calculating power consumption of a logic design by using a computer or a processor, the method comprising:

programming the logic design into a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

providing a variable sampling rate that defines a number of cycles of a clock driving the logic design for which state transition activity data for each logic gate and register in the logic design will be collected during a sample period, the state transition activity data comprising a number of state transitions and duty cycle for each logic gate and register in the logic design during the sample period, where state transitions comprise transitions between logic level high and logic level low, and the sampling rate applied during a high power operation of the logic design being greater than the sampling rate applied during a low power operation;

emulating the logic design in said hardware logic emulation system;

running application software on the logic design being emulated in the hardware logic emulation system during the sample period;

collecting said state transition activity data in accordance with the variable sampling rate;

feeding design hierarchy information of the logic design to a power calculation software tool running in the computer or processor;

feeding the transition activity data to the power calculation software tool; and

calculating static and dynamic power consumed by at least a portion of the logic design using the design hierarchy information and the state transition activity data and the duty cycle collected during each of the sample period, wherein the static and dynamic power is calculated by the power calculation software tool; and

changing the logic design to optimize power consumption.

22. The method of claim 21 wherein each of the plurality of integrated circuits comprise a programmable logic device.

23. The method of claim 21 wherein each of the plurality of integrated circuits comprise a processor chip.

24. The method of claim 21 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

25. A method for calculating power consumption of a logic design by using a computer or a processor, the method comprising:

defining an event, said event defined by a triggering condition comprising predetermined logic states for specified nodes in the logic design;

defining a sampling window, said sampling window comprising a plurality of segments, each of said segments defining how many cycles of a clock driving the logic design for which transition activity data for each logic gate and register in the logic design will be collected, the state transition activity data comprising a number of state transitions and duty cycle for each logic gate and register in the logic design during the power evaluation period, where state transitions comprise transitions between logic level high and logic level low;

emulating the logic design in a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

running application software on the logic design being emulated in the hardware logic emulation system during the plurality of segments;

when said event occurs during the emulation of the logic design, collecting said state transition activity data;

feeding design hierarchy information of the logic design to a power calculation software tool running in the computer or processor;

feeding the transition activity data to the power calculation software tool; and

calculating static and dynamic power consumed by at least a portion of the logic design using the design hierarchy information and the state transition activity data and the duty cycle collected during each of said plurality of segments,

wherein the static and dynamic power is calculated by the power calculation software tool; and

changing the logic design to optimize power consumption.

26. The method of claim 25 wherein each of the plurality of integrated circuits comprise a programmable logic device.

27. The method of claim 25 wherein each of the plurality of integrated circuits comprise a processor chip.

28. The method of claim 25 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

29. A method for calculating a selected characteristic of a logic design by using a computer or a processor, the method comprising:

defining a predetermined event, said predetermined event defined by a triggering condition comprising predetermined logic states for specified nodes in the logic design;

defining a sampling window, said sampling window comprising a plurality of segments, each of said defining how many cycles of a clock driving the logic design for which state transition activity data for each logic gate and register in the logic design will be collected, the state transition activity data comprising a number of state transitions and duty cycle for each logic gate and register in the logic design during the power evaluation period, where state transitions comprise transitions between logic level high and logic level low;

running application software on the logic design being emulated in the hardware logic emulation system during the sampling window;

emulating the logic design in a hardware logic emulation system comprised of a plurality of interconnected programmable integrated circuits;

when said predetermined event occurs during the emulation of the logic design, collecting said state transition activity data;

feeding design hierarchy information of the logic design to a software tool running in the computer or processor;

feeding the transition activity data to the software tool;

calculating the selected characteristic of at least a portion of the logic design using the design hierarchy information and the state transition activity data and the duty cycle collected during each of the plurality of samples, wherein the selected characteristic is calculated by the software tool;

displaying a waveform of the selected characteristic of the logic design; and

changing the logic design to optimize power consumption.

30. The method of claim 29, wherein the selected characteristic is power consumed by the logic design.

31. The method of claim 29 wherein each of the plurality of integrated circuits comprise a programmable logic device.

32. The method of claim 29 wherein each of the plurality of integrated circuits comprise a processor chip.

33. The method of claim 29 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.

34. An apparatus for calculating power consumption of a logic design comprising:

a processor running a power calculation software tool; and

an interface receiving;

i) transition activity data produced using a number of state transitions and duty cycle from a hardware logic emulation system, and

ii) design hierarchy information of the logic design from the hardware logic emulation system;

wherein the hardware logic emulation system is comprised of a plurality of interconnected programmable integrated circuits and emulates the logic design for application software running on the emulated logic design,

wherein the hardware logic emulation system collects the number of state transitions between logic level high and logic level low and the duty cycle for each logic gate and register in the logic design for state transitions taking place during a sample period of the application software running on the emulated logic design, said sample period comprising a predetermined number of clock cycles,

wherein the power calculation software tool calculates static and dynamic power for the software application running on the emulated logic design during the sample period consumed by at least a portion of the logic design using the design hierarchy information and the number of state transitions and the duty cycle for each of the logic gates and the registers in the logic design that was collected during said sample period changing the logic design to optimize power consumption.

35. The method of claim 34 wherein the application software is software that will run in a target system including the logic design after the logic design is fabricated.