Method of lifting off and fabricating array substrate for liquid crystal display device using the same

• US 8,454,847 B2
• Filed: 06/21/2011
• Issued: 06/04/2013
• Est. Priority Date: 07/20/2007
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Kwack, Hee-Young, Hong, Hyun-Seok, Lim, Joo-Soo, Kim, Hong-Sik
• Primary Examiner(s): Tran, Binh X
• Application Number:
  US13/165,466
• Publication Number:
  US 20110250532A1
• Time in Patent Office: 714 Days
• Field of Search: 216/23, 216/40, 216/47, 216/75
• US Class Current: 216/23
• CPC Class Codes: G02F 1/13625 Patterning using multi-mask exposure
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A method of lifting off includes forming a first material layer on a substrate; forming a photoresist pattern including first and second holes and on the first material layer; patterning the first material layer using the photoresist pattern as a patterning mask to form a material pattern having first and second grooves within the material pattern, the first and second grooves corresponding to the first and second holes, respectively; forming a second material layer on an entire surface of the substrate including the photoresist pattern and the first and second grooves; and removing the photoresist pattern and the second material layer on the photoresist pattern at the same time, wherein a portion of the material pattern between the first and second grooves and portions of the material pattern at sides of the first and second grooves constitute a line as a whole.

Claims

1. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate line and a gate electrode on a substrate, the substrate having a display region and first to fourth non-display regions at periphery of the display region, the gate electrode being disposed in the display region;

forming a data line, a data pad, a semiconductor layer, a source electrode and a drain electrode on the substrate, the data line crossing the gate line, the data pad disposed at one end of the data line and in the first non-display region, the semiconductor layer disposed over the gate electrode, the source electrode connected to the data line and disposed on the semiconductor layer, the drain electrode spaced apart from the source electrode and disposed on the semiconductor layer;

forming an insulating material layer over an entire surface of the substrate including the data line, the data pad, the source electrode and the drain electrode;

forming a first photoresist pattern corresponding to the source and drain electrode, and a second photoresist pattern having first and second holes, the first photoresist pattern exposing a portion of the drain electrode, the first and second holes respectively corresponding to first and second portions of the data pad;

patterning the insulating material layer by using the first and second photoresist patterns as a patterning mask to form a passivation layer exposing the portion of the drain electrode and a first passivation pattern having first and second grooves, the first and second grooves exposing the first and second portions of the data pad, respectively;

forming a conductive material layer over an entire surface of the substrate including the first and second photoresist patterns, the passivation layer and the first passivation pattern; and

removing the first and second photoresist patterns and the conductive material layer on the first and second photoresist patterns at the same time by a lifting off process.

2. The method according to claim 1, wherein the conductive material layer is a transparent conductive material or an opaque metallic conductive material.

3. The method according to claim 1, wherein each of the data pad and the second, third and fourth non-display regions has a width greater than 200 micrometers.

4. The method according to claim 1, wherein the step of forming the first and second photoresist patterns comprises forming a third photoresist pattern having third and fourth holes, the third and fourth holes corresponding to third and fourth portions, respectively, in each of the second, third and fourth non-display regions;

the step of patterning the insulating material layer comprises forming a second passivation pattern having third and fourth grooves, the third and fourth grooves exposing the third and fourth portions, respectively, in each of the second, third and fourth non-display regions; and

the step of lifting off comprises removing the third photoresist pattern and the conductive material layer on the third photoresist pattern.

5. The method according to claim 4, wherein each of the first, second, third and fourth grooves includes one of a bar shape, a saw tooth shape, a cross shape, and a shape.

6. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a gate line and a gate pad on a substrate, the gate pad disposed at one end of the gate line;

sequentially forming a gate insulating layer, an intrinsic amorphous silicon layer, an impurity-doped amorphous silicon layer and a metal layer over an entire surface of the substrate including the gate line and the gate pad;

patterning the metal layer, the impurity-doped amorphous silicon layer, the intrinsic amorphous silicon layer and the gate insulating layer to expose the gate pad and form a data line crossing the gate line to define a pixel region and a data pad disposed at one end of the data line;

forming a conductive material layer over an entire surface of the substrate including the data line and the data pad;

forming a first photoresist pattern including first and second holes and a second photoresist pattern including third and fourth holes, the first and second holes corresponding to first and second portions of the gate pad, respectively, the third and fourth holes corresponding to third and fourth portions of the data pad, respectively;

patterning the conductive material layer using the first and second photoresist patterns as a patterning mask to form a first conductive material pattern having first and second grooves and a second conductive material pattern having third and fourth grooves, the first and second grooves exposing the first and second portions, respectively, of the gate pad, the third and fourth grooves exposing the third and fourth portions, respectively, of the data pad;

forming a passivation layer over an entire surface of the substrate including the first and second photoresist patterns and the first, second, third and fourth grooves; and

removing the first and second photoresist patterns and the passivation layer on the first and second photoresist patterns at the same time by a lifting off process.

7. The method according to claim 6, wherein the conductive material layer is a transparent conductive material or an opaque metallic conductive material.

8. The method according to claim 6, wherein the step of forming the gate line and the gate pad comprises forming a gate electrode connected to the gate line;

the step of patterning the metal layer, the impurity-doped amorphous silicon layer, the intrinsic amorphous silicon layer and the gate insulating layer comprises forming an intrinsic amorphous silicon pattern, an impurity-doped amorphous silicon pattern and a metal pattern stacked over the gate electrode;

the step of forming the first and second photoresist patterns comprises forming a third photoresist pattern exposing a center of the metal pattern;

the step of patterning the conductive material layer comprises removing the exposed metal pattern and a portion of the impurity-doped amorphous silicon pattern and forming a pixel electrode in the pixel region and connected to a portion of the metal pattern; and

the step of removing the first and second photoresist patterns and the passivation layer comprises removing the third photoresist pattern and the passivation layer on the third photoresist pattern.

9. The method according to claim 6, wherein each of the first, second, third and fourth grooves includes one of a bar shape, a saw tooth shape, a cross shape, and a shape.

10. The method according to claim 6, wherein each of the gate pad and the data pad has a width greater than 200 micrometers.

11. The method according to claim 10, wherein the step of forming the passivation layer by a sputtering method.