Low frequency CMUT with thick oxide

• US 8,455,289 B1
• Filed: 12/02/2011
• Issued: 06/04/2013
• Est. Priority Date: 12/02/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Johnson, Peter, Adler, Steven, Wygant, Ira Oaktree
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/309,853
• Publication Number:
  US 20130140704A1
• Time in Patent Office: 550 Days
• Field of Search: 257/415, 257/416, 257/595, 257/E27.016, 310/12.03, 310/311, 600/300, 600/404, 600/437, 438/48, 438/50, 438/51, 438/53
• US Class Current: 438/53
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: G01N 29/2406 Electrostatic or capacitive probes, e.g. electret or cMUT-probes

Abstract

A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.

Claims

1. A method of forming a semiconductor transducer comprising:

providing semiconductor substrate having top and bottom surfaces wherein the top surface lies in a plane;

growing approximately a 5.15 micrometer thick oxide layer on both the top and bottom surfaces of the semiconductor wafer using a high-pressure oxidation (HIPOX) process;

wherein the 5.15 micrometer thick oxide layer is grown at a temperature in range of 900°

C. to 1200°

C. with an operating pressure of 10 to 20 atmospheres;

forming a patterned photoresist layer on the thick oxide layer on the top surface of the semiconductor substrate;

etching the thick oxide layer, exposing the top surface of the semiconductor substrate and forming a post structure on the top surface of the semiconductor substrate from the thick oxide layer, wherein the post structure having a top surface, being non-conductive, and laterally surrounding a cell region of the top surface of the substrate has no portion of the post structure lying below the plane of the top surface of the semiconductor substrate;

wherein etching the thick oxide layer comprises;

etching approximately 4.65 micrometers of the approximately 5.15 micrometer thick layer utilizing a non-polymerizing plasma etch, wherein the slope of the side wall at the end of the non-polymerizing etch is approximately 80°

, making the opening slightly larger at the top than at the bottom of the thick oxide layer; and

removing the remaining approximately 0.5 micrometers of the thick oxide layer with a wet etchant that is highly or completely selective to silicon, thus leaving the cell region on the top surface of the semiconductor substrate without damage;

forming a non-conductive structure that touches the cell region of the top surface of the semiconductor substrate; and

forming a conductive structure that touches the top surface of the post structure and lies directly vertically over the non-conductive structure to form a cavity that lies vertically between the non-conductive structure and the conductive structure.

2. The method of claim 1 wherein the post structure laterally surrounds and touches the non-conductive structure.

3. The method of claim 2 wherein the cavity is under a vacuum.

4. The method of claim 3 and further comprising forming a metal bond pad structure that touches the bottom surface of the substrate.

5. The method of claim 4 wherein no conductive structure extends through the post structure.

6. The method of claim 5 wherein the conductive structure includes:

a single-crystal silicon structure; and

a metal plate that touches the single-crystal silicon structure.

7. The method of claim 3 and further comprising forming a bond pad opening that extends completely through the post structure to expose the substrate.

8. The method of claim 7 and further comprising forming a conductive bond pad structure that lies in the bond pad opening to touch the substrate.

9. The method of claim 8 wherein the conductive structure includes:

a single-crystal silicon structure; and

a metal plate that touches the single-crystal silicon structure.

10. The method of claim 2 wherein no non-conductive structure lies directly vertically between the cell region of the top surface of the substrate and the bottom surface of the substrate.