Methods of forming features of integrated circuitry

• US 8,455,341 B2
• Filed: 09/02/2010
• Issued: 06/04/2013
• Est. Priority Date: 09/02/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Russell, Stephen W., Armstrong, Kyle A.
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US12/874,781
• Publication Number:
  US 20120058633A1
• Time in Patent Office: 1,006 Days
• Field of Search: 438/585, 438/593
• US Class Current: 438/585
• CPC Class Codes: G03F 7/0035 Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

Methods of forming features such as word lines of memory circuitry are disclosed. One such method includes forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area. Thereafter, a subsequent feature pattern is formed which extends from the target array area into the other of the first or second periphery area. The initial and subsequent feature patterns may be used in forming features in an underlying material which extend from the target area to the first and second periphery areas. Other embodiments are disclosed.

Claims

1. A method of forming features of integrated circuitry, comprising:

forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area;

after forming the initial pitch multiplied feature pattern, forming a subsequent feature pattern extending from the target area into the other of the first or second periphery area; and

using the initial and subsequent feature patterns in forming features in underlying material which extend from the target area to the first and second periphery areas.

2. The method of claim 1 wherein the initial pitch multiplied feature pattern comprises a word line pattern, the target area comprises a memory array area, the first and second periphery areas are control circuitry connection areas, the subsequent feature pattern comprises a subsequent word line pattern, and the underlying material comprises a gate stack.

3. The method of claim 1 wherein forming the initial pitch multiplied feature pattern comprises lateral trimming of masking material from which the initial pitch multiplied feature pattern is made.

4. The method of claim 1 wherein the subsequent feature pattern is formed to be pitch multiplied within the target area.

5. The method of claim 4 wherein the subsequent feature pattern is formed to self-align relative to the initial pitch multiplied feature pattern in the target area.

6. The method of claim 5 wherein the subsequent feature pattern is formed to self-align between spacer material deposited laterally over sidewalls of the initial pitch multiplied feature pattern.

7. The method of claim 1 wherein said using comprises a subsequent pitch multiplication of the initial and subsequent feature patterns.

8. The method of claim 1 wherein said using comprises:

transferring the initial and subsequent feature patterns to a first hard-mask;

pitch multiplying the transferred initial and subsequent feature patterns;

transferring the transferred pitch multiplied initial and subsequent feature patterns to a second hard-mask; and

subsequently using the second hard-mask as an etch mask in forming the features in the underlying material by etching.

9. The method of claim 1 wherein the pitch multiplication of the initial pitch multiplied feature pattern is from about 4F to about 2F, where 1F is a minimum final feature width.

10. The method of claim 9 wherein the subsequent feature pattern is formed to be effectively pitch multiplied to about 2F within the target area.

11. A method of forming features of integrated circuitry comprising a target area having features which extend outwardly there-from to opposing first and second periphery areas on opposing sides of the target area, comprising:

forming an initial feature pattern in a first hard-mask, the initial feature pattern comprising an initial pattern of lines which alternate every other line in extending from the target area to alternating of the first and second periphery areas;

using the initial feature pattern in forming a subsequent feature pattern in a second hard-mask, the subsequent feature pattern comprising a subsequent pattern of lines which alternate in pairs of two immediately adjacent lines in extending from the target area to alternating of the first and second periphery areas; and

transferring the subsequent feature pattern in the second hard-mask to an underlying material overlying the target area and the first and second periphery areas.

12. The method of claim 11 wherein the initial feature pattern comprises a word line pattern, the target area comprises a memory array area, the first and second periphery areas are control circuitry connection areas, the subsequent feature pattern comprises a subsequent word line pattern, and the underlying material comprises a gate stack.

13. The method of claim 11 comprising forming the two immediately adjacent lines within individual of the pairs to comprise different minimum widths outside of the target area.

14. The method of claim 11 comprising forming the two immediately adjacent lines within individual of the pairs to be equally spaced from one another along their respective lengths outside of the target area.

15. The method of claim 14 comprising forming immediately adjacent of the pairs to be equally spaced from one another along their respective lengths outside of the target area.

16. The method of claim 11 comprising:

forming the two immediately adjacent lines within individual of the pairs to be equally spaced from one another at a first spacing along their respective lengths outside of the target area; and

forming immediately adjacent of the pairs to be equally spaced from one another at a second spacing along their respective lengths outside of the target area, the second spacing being greater than the first spacing.

17. The method of claim 11 wherein forming the initial feature pattern comprises pitch multiplication.

18. The method of claim 11 wherein said using of the initial feature pattern comprises pitch multiplication.

19. The method of claim 11 wherein forming the initial feature pattern comprises initial pitch multiplication, and said using of the initial feature pattern comprises subsequent pitch multiplication.

20. The method of claim 19 wherein the initial pitch multiplication is from about 4F to about 2F and the subsequent pitch multiplication is from said about 2F to about 1F, where 1F is a minimum final feature width.

21. A method of forming features of integrated circuitry comprising a target area having features which extend outwardly there-from to opposing first and second periphery areas on opposing sides of the target area, comprising:

using three, and only three, photomasking steps in defining longitudinal outlines of pitch quadrupled features in a hard-mask received within the target area and which individually extend to individual of the opposing first and second periphery areas;

using a first of the three photomasking steps in forming an initial pitch multiplied feature pattern extending from the target area into only one of the first or second periphery areas; and

transferring the longitudinal outlines of the pitch quadrupled features in the hard-mask to an underling material overlying the target area and the first and second periphery areas.

22. The method of claim 21 wherein the pitch quadrupled features are word lines, the target area comprises a memory array area, the first and second periphery areas are control circuitry connection areas, and the underlying material comprises a gate stack.

23. The method of claim 21 comprising using an intermediate of the three photomasking steps to form an intermediate feature pattern extending from the target area into only one of the first or second periphery areas.

24. The method of claim 21 comprising using a third of the three photomasking steps to form a tertiary feature pattern extending from the target area into the first and second periphery areas.

25. A method of forming features of integrated circuitry comprising a target area having features which extend outwardly there-from to opposing first and second periphery areas on opposing sides of the target area, comprising:

forming an initial feature pattern extending from the target area into the first and second periphery areas, the initial feature pattern comprising an initial pattern of lines;

forming spacer material over the initial feature pattern in the target area and in the first and second periphery areas;

forming fill material over the spacer material in the target area and in the first and second periphery areas;

forming an etch mask over the fill material, the etch mask comprising individual mask lines having opposing longitudinal edges within the first and second periphery areas, one of the edges of the individual mask lines overlying an individual of the lines of the initial pattern of lines, the other edge of the individual mask lines overlying fill material received between spacer material between immediately adjacent of the lines of the initial pattern of lines;

using the etch mask, etching the fill material to form a subsequent feature pattern extending from the target area into the first and second periphery areas, the subsequent feature pattern comprising a subsequent pattern of lines individually having opposing longitudinal edges, one of the edges of the individual of the subsequent pattern of lines self-aligning in the first and second periphery areas along one longitudinal edge of spacer material received laterally on individual of the lines of the initial pattern of lines, the other of the edge of the individual of the subsequent pattern of lines in the first and second periphery areas being defined by the other edge of the individual mask lines overlying fill material received between spacer material between immediately adjacent of the lines of the initial pattern of lines;

after forming the subsequent feature pattern, removing elevationally exposed spacer material from the target area and the first and second periphery areas;

after removing the elevationally exposed spacer material from the target area and the first and second periphery areas, transferring the initial and subsequent feature patterns to an underlying hard-mask material; and

transferring the initial and subsequent feature patterns in the hard-mask material to material underlying the hard-mask material to form features in said underlying material.

26. The method of claim 25 wherein the initial feature pattern comprises a word line pattern, the target area comprises a memory array area, the first and second periphery areas are control circuitry connection areas, the subsequent feature pattern comprises a subsequent word line pattern, and the underlying material comprises a gate stack.

27. A method of forming features of integrated circuitry comprising a target area having features which extend outwardly there-from to opposing first and second periphery areas on opposing sides of the target area, comprising:

forming a first feature pattern over a first hard-mask material received over a second hard-mask material received over an underlying material, the first feature pattern extending from the target area into only one of the first or second periphery areas, the first feature pattern comprising a first pattern of lines having minimum lateral width of about 4F separated by about 4F spaces where about 1F is a minimum final feature width;

laterally trimming the first pattern of lines to form a second feature pattern extending from the target area into only said one first or second periphery area, the second feature pattern comprising a second pattern of lines having minimum lateral width of about 2F separated by about 6F spaces;

forming first spacer material to a thickness of about 2F over the second feature pattern and over the other of the first and second periphery areas;

forming first fill material over the first spacer material in the target area and in the first and second periphery areas;

forming a third feature pattern with the first fill material, the third feature pattern comprising first fill material over first spacer material, the third feature pattern extending from the target area into only said other first or second periphery area, the third feature pattern comprising a third pattern of lines which self-align and alternate with the second pattern of lines in the target area and have lateral width of about 2F in the target area, the third pattern of lines having minimum lateral width of about 4F separated by about 4F spaces in said other first or second periphery area;

after forming the third feature pattern, removing elevationally exposed first spacer material from the target area and said one first or second periphery area;

after removing the elevationally exposed first spacer material from the target area and said one first or second periphery area, transferring the second and third feature patterns to the first hard-mask material;

laterally trimming the second and third pattern of lines in the first hard-mask material to form a fourth feature pattern, the fourth feature pattern comprising a fourth pattern of lines having minimum lateral width of about 1F separated by about 3F spaces within the target area;

forming second spacer material to a thickness of about 1F over the fourth feature pattern in the target area and the first and second periphery areas;

forming second fill material over the second spacer material in the target area and in the first and second periphery areas;

forming a fifth feature pattern with the second fill material, the fifth feature pattern comprising second fill material over second spacer material, the fifth feature pattern extending from the target area into the first and second periphery areas, the fifth feature pattern comprising a fifth pattern of lines which self-align and alternate with the fourth pattern of lines of the first hard-mask material in the target area and have lateral width of about 1F in the target area;

after forming the fifth feature pattern, removing elevationally exposed second spacer material from the target area and the first and second periphery areas;

after removing the elevationally exposed second spacer material from the target area and the first and second periphery areas, transferring the fourth and fifth feature patterns to the second hard-mask material; and

transferring the fourth and fifth feature patterns in the second hard-mask material to the underlying material to form lines in the underlying material within the target area having minimum lateral width of about 1F.

28. The method of claim 27 wherein the first feature pattern comprises a first word line pattern, the target area is a memory array area, the first and second periphery areas are control circuitry connection areas, the second feature pattern comprises a second word line pattern, the third feature pattern comprises a third word line pattern, the fourth feature pattern comprises a fourth word line pattern, the fifth feature pattern comprises a fifth word line pattern, and the underlying material comprises a gate stack.