Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same

• US 8,455,854 B2
• Filed: 02/09/2007
• Issued: 06/04/2013
• Est. Priority Date: 02/20/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Choong-Rae, Cho, Sung-Il, Yoo, In-Kyeong, Lee, Eun-Hong, Moon, Chang-Wook
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US11/704,365
• Publication Number:
  US 20070257257A1
• Time in Patent Office: 2,307 Days
• Field of Search: 257/421, 257/427, 257/E29.167, 257/E29.323, 257/E21.665, 257/E21.009, 257/E21.272, 257/4
• US Class Current: 257/4
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.

Claims

1. A nonvolatile memory device, comprising:

a lower electrode;

an amorphous alloy metal oxide layer directly disposed on the lower electrode; and

a upper electrode disposed on the amorphous alloy metal oxide layer,

wherein the amorphous alloy metal oxide layer is a memory node and formed of a variable resistance material,

wherein the amorphous alloy metal oxide layer includes at least a first transition metal and a second metal having a different crystalline characteristic from the first transition metal,

wherein the first transition metal is one of Ni, Ti, Hf, Zr, W, Co, and Nb, and wherein the second metal is one of Al and In.

2. The nonvolatile memory device of claim 1, wherein at least one of the lower and upper electrodes forms a Schottky junction with the amorphous alloy metal oxide layer.

3. The nonvolatile memory device of claim 2, wherein the amorphous alloy metal oxide layer is formed of n-type oxide and one of the lower and upper electrodes is formed of one of Pt, Ir, Ru, and an oxide of Pt, Ir, and Ru.

4. The nonvolatile memory device of claim 2, wherein the amorphous alloy metal oxide layer is formed of a p-type oxide and one of the lower and upper electrodes is formed of one of Ti and Ag.

5. The nonvolatile memory device of claim 1, wherein the upper electrode is connected to a diode structure.

6. A method of manufacturing a nonvolatile memory device, comprising:

forming a lower electrode;

forming an amorphous alloy metal oxide layer directly on the lower electrode; and

forming an upper electrode on the amorphous metal alloy layer,

wherein the amorphous alloy metal oxide layer is a memory node and formed of a variable resistance material,

wherein the amorphous alloy metal oxide layer includes at least a first transition metal and a second metal having a different crystalline characteristic from the first transition metal,

wherein the first transition metal is one of Ni, Ti, Hf, Zr, W, Co, and Nb, and

wherein the second metal is one of Al and In.

7. The method of claim 6, wherein at least one of the lower and upper electrodes forms a Schottky-junction with the amorphous alloy metal oxide layer.

8. The method of claim 7, wherein the amorphous alloy metal oxide layer is formed of n-type oxide and one of the lower and upper electrodes is formed of one of Pt, Ir, Ru, and an oxide of Pt, Ir, and Ru.

9. The method of claim 7, wherein the amorphous alloy metal oxide layer is formed of a p-type oxide and one of the lower and upper electrodes is formed of one of Ti and Ag.

10. The method of claim 6, further comprising connecting the upper electrode to a diode structure.