Power MISFET semiconductor device

• US 8,455,943 B2
• Filed: 07/13/2011
• Issued: 06/04/2013
• Est. Priority Date: 04/09/2008
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakazawa, Yoshito, Matsuura, Hitoshi
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/181,816
• Publication Number:
  US 20110266617A1
• Time in Patent Office: 692 Days
• Field of Search: 257/330, 257/471, 257/476, 257/E29.262
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

Claims

1. A semiconductor device including a power MISFET, comprising:

a semiconductor substrate having a first conductivity type;

a semiconductor layer formed over the semiconductor substrate and having the first conductivity type;

a channel region of the power MISFET formed in the semiconductor layer and having a second conductivity type opposite to the first conductivity type;

a trench penetrating through the channel region and reaching the semiconductor layer;

a gate insulating film of the power MISFET formed over an inner wall of the trench;

a gate electrode of the power MISFET formed over the gate insulating film and filled in the trench;

a source region of the power MISFET formed over the channel region, having the first conductivity type and being contiguous to the trench;

an insulating film formed over the gate electrode and the source region;

a contact hole formed in the semiconductor layer, arranged apart from the trench and having a depth greater than that of the source region;

a body contact region formed below the bottom portion of the contact hole, being contiguous to the channel region and having the second conductivity type;

a first metal film formed over the insulating film, filling in the contact hole and electrically connected to the source region and the body contact region; and

a second metal film formed over a rear surface of the semiconductor substrate and having function as a drain electrode of the power MISFET,

wherein a first semiconductor region is formed below the body contact region, is contiguous to the body contact region and has the second conductivity type, and

wherein an impurity concentration of the first semiconductor region is lower than an impurity concentration of the body contact region.

2. A semiconductor device according to the claim 1,

wherein a depth of the first semiconductor region is shallower than the bottom portion of the trench.

3. A semiconductor device according to the claim 1,

wherein the impurity concentration of the first semiconductor region is higher than an impurity concentration of the channel region.

4. A semiconductor device according to the claim 1,

wherein the first conductivity type is n-type, and

wherein the second conductivity type is p-type.

5. A semiconductor device according to the claim 1,

wherein the gate electrode includes a poly silicon film.

6. A semiconductor device according to the claim 1,

wherein the gate electrode is formed in the trench and is not formed between the source region and the insulating film.

7. A semiconductor device according to the claim 1,

wherein the semiconductor layer has a first epitaxial semiconductor layer and a epitaxial second semiconductor layer formed over the first epitaxial semiconductor layer, and

wherein an impurity concentration of the first epitaxial semiconductor layer is higher than an impurity concentration of the second epitaxial semiconductor layer.

8. A semiconductor device according to the claim 7,

wherein the bottom of the trench reaches at the first semiconductor layer.

9. A semiconductor device including a power MISFET, comprising:

a semiconductor substrate having a first conductivity type;

a semiconductor layer formed over the semiconductor substrate and having the first conductivity type;

a channel region of the power MISFET formed in the semiconductor layer and having a second conductivity type opposite to the first conductivity type;

a trench penetrating through the channel region and reaching the semiconductor layer;

a gate insulating film of the power MISFET formed over an inner wall of the trench;

a gate electrode of the power MISFET formed over the gate insulating film and filled in the trench;

a source region of the power MISFET formed over the channel region, having the first conductivity type and being contiguous to the trench;

an insulating film formed over the gate electrode and the source region;

a contact hole formed in the semiconductor layer, arranged apart from the trench and having a depth greater than that of the source region;

a body contact region formed below the bottom portion of the contact hole, being contiguous to the channel region and having the second conductivity type;

a first metal film formed over the insulating film, filling in the contact hole and electrically connected to the source region and the body contact region; and

a second metal film formed over a rear surface of the semiconductor substrate and having function as a drain electrode of the power MISFET,

wherein a first semiconductor region is formed below the body contact region, is contiguous to the body contact region and has the second conductivity type,

wherein an impurity concentration of the first semiconductor region is lower than an impurity concentration of the body contact region,

wherein a depth of the first semiconductor region is shallower than the bottom portion of the trench, and

wherein the impurity concentration of the first semiconductor region is higher than an impurity concentration of the channel region.

10. A semiconductor device according to the claim 9,

wherein the first conductivity type is n-type, and

wherein the second conductivity type is p-type.

11. A semiconductor device according to the claim 9,

wherein the gate electrode includes a poly silicon film.

12. A semiconductor device according to the claim 9,

wherein the gate electrode is formed in the trench and is not formed between the source region and the insulating film.

13. A semiconductor device according to the claim 9,

wherein the semiconductor layer has a first epitaxial semiconductor layer and a second epitaxial semiconductor layer formed over the first epitaxial semiconductor layer, and

wherein an impurity concentration of the first epitaxial semiconductor layer is higher than an impurity concentration of the second epitaxial semiconductor layer.

14. A semiconductor device according to the claim 13,

wherein the bottom of the trench reaches at the first semiconductor layer.