High power semiconductor device

• US 8,455,997 B2
• Filed: 12/02/2011
• Issued: 06/04/2013
• Est. Priority Date: 04/13/2011
• Status: Active Grant

• Current Assignee: Arigna Technology Limited (Atlantic IP Services Limited)
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Nakanishi, Hidetoshi, Miyazaki, Yuji
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US13/309,754
• Publication Number:
  US 20120261811A1
• Time in Patent Office: 550 Days
• Field of Search: 257/712, 257/717, 257/E23.101
• US Class Current: 257/712
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/19107 off-chip wires

Abstract

A semiconductor device includes an insulating substrate, a metal pattern formed on the insulating substrate, a power terminal bonded onto the metal pattern, and a plurality of power chips bonded onto the metal pattern. The plurality of power chips are all separated from the power terminal by a distance sufficient to thermally isolate the plurality of power chips from the power terminal.

Claims

1. A semiconductor device comprising:

an insulating substrate;

a metal pattern formed on said insulating substrate;

a power terminal bonded onto said metal pattern;

an exposed solder pattern without any electronic component bonded thereto or connected thereto, the exposed solder pattern bonded onto the metal pattern between the power terminal and the plurality of power chips;

a plurality of power chips bonded onto said metal pattern;

wherein said plurality of power chips are all separated from said power terminal by a distance sufficient to thermally isolate said plurality of power chips from said power terminal.

2. The semiconductor device according to claim 1, wherein a heat sink is bonded onto said exposed solder pattern between said power terminal and said plurality of power chips.

3. The semiconductor device according to claim 1, wherein:

said metal pattern is formed of copper;

each of said plurality of power chips is an insulated gate bipolar transistor (IGBT) chip or a diode chip; and

the distance between said power terminal and the closest of said plurality of power chips is 5 mm or more.