Post passivation interconnection schemes on top of the IC chips

• US 8,456,013 B2
• Filed: 03/24/2011
• Issued: 06/04/2013
• Est. Priority Date: 10/15/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US13/071,203
• Publication Number:
  US 20110175227A1
• Time in Patent Office: 803 Days
• Field of Search: 257/690, 257/691, 257/700, 257/773, 257/774, 257/E21.575, 438614-616, 438/622, 438/631, 438/637, 438/638, 438/107, 438/110, 438/624
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said first dielectric layer;

a second interconnecting structure over said silicon substrate and in said first dielectric layer;

an insulating layer over said dielectric layer;

a third interconnecting structure over said insulating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a power is adapted to be provided to said third interconnecting structure, wherein said third interconnecting structure is provided by a topmost metal layer of interconnecting lines of said chip.

2. The chip of claim 1, wherein said power is output from a voltage regulator.

3. The chip of claim 1, wherein said insulating layer comprises a nitride.

4. The chip of claim 1, wherein said insulating layer comprises silicon nitride.

5. The chip of claim 1, wherein said insulating layer comprises an oxide.

6. The chip of claim 1, wherein said insulating layer comprises silicon oxide.

7. The chip of claim 1, wherein said first interconnecting structure comprises an electroplated metal.

8. The chip of claim 1, wherein said first interconnecting structure comprises a damascene metal.

9. The chip of claim 1, wherein said third interconnecting structure comprises copper.

10. The chip of claim 1, wherein said third interconnecting structure comprises gold.

11. The chip of claim 1 further comprising a third dielectric layer over said insulating layer, wherein said third dielectric layer comprises a portion on said top surface of said third interconnecting structure.

12. The chip of claim 11, wherein said third dielectric layer comprises a polymer.

13. The chip of claim 1 further comprising a third dielectric layer over said insulating layer, wherein said third dielectric layer comprises a portion between said third interconnecting structure and said insulating layer, wherein said third dielectric layer comprises a polymer.

14. A chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said first dielectric layer;

a second interconnecting structure over said silicon substrate and in said first dielectric layer;

an insulating layer over said dielectric layer; and

a third interconnecting structure over said insulating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a ground is adapted to be provided to said third interconnecting structure, wherein said third interconnecting structure is provided by a topmost metal layer of interconnecting lines of said chip.

15. The chip of claim 14, wherein said insulating layer comprises a nitride.

16. The chip of claim 14, wherein said insulating layer comprises silicon nitride.

17. The chip of claim 14, wherein said insulating layer comprises an oxide.

18. The chip of claim 14, wherein said insulating layer comprises silicon oxide.

19. The chip of claim 14, wherein said first interconnecting structure comprises an electroplated metal.

20. The chip of claim 14, wherein said first interconnecting structure comprises a damascene metal.

21. The chip of claim 14, wherein said third interconnecting structure comprises copper.

22. The chip of claim 14, wherein said third interconnecting structure comprises gold.

23. The chip of claim 15 further comprising a third dielectric layer over said insulating layer, wherein said third dielectric layer comprises a portion on said top surface of said third interconnecting structure.

24. The chip of claim 23, wherein said third dielectric layer comprises a polymer.

25. The chip of claim 14 further comprising a third dielectric layer over said insulating layer, wherein said third dielectric layer comprises a portion between said third interconnecting structure and said insulating layer, wherein said third dielectric layer comprises a polymer.

26. A chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said first dielectric layer;

a second interconnecting structure over said silicon substrate and in said first dielectric layer;

a passivation layer over said first dielectric layer; and

a third interconnecting structure over said passivation layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a power is adapted to be provided to said third interconnecting structure.

27. The chip of claim 26, wherein said power is output from a voltage regulator.

28. The chip of claim 26, wherein said passivation layer comprises a nitride.

29. The chip of claim 26, wherein said passivation layer comprises silicon nitride.

30. The chip of claim 26, wherein said passivation layer comprises an oxide.

31. The chip of claim 26, wherein said passivation layer comprises silicon oxide.

32. The chip of claim 26, wherein said first interconnecting structure comprises an electroplated metal.

33. The chip of claim 26, wherein said first interconnecting structure comprises a damascene metal.

34. The chip of claim 26, wherein said third interconnecting structure comprises copper.

35. The chip of claim 26, wherein said third interconnecting structure comprises gold.

36. The chip of claim 26 further comprising a third dielectric layer over said passivation layer, wherein said third dielectric layer comprises a portion on said top surface of said third interconnecting structure.

37. The chip of claim 36, wherein said third dielectric layer comprises a polymer.

38. The chip of claim 26 further comprising a third dielectric layer over said passivation layer, wherein said third dielectric layer comprises a portion between said third interconnecting structure and said passivation layer, wherein said third dielectric layer comprises a polymer.

39. A chip comprising:

a silicon substrate;

a first dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said first dielectric layer;

a second interconnecting structure over said silicon substrate and in said first dielectric layer;

a passivation layer over said first dielectric layer; and

a third interconnecting structure over said passivation layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a ground is adapted to be provided to said third interconnecting structure.

40. The chip of claim 39, wherein said passivation layer comprises a nitride.

41. The chip of claim 39, wherein said passivation layer comprises silicon nitride.

42. The chip of claim 39, wherein said passivation layer comprises an oxide.

43. The chip of claim 39, wherein said passivation layer comprises silicon oxide.

44. The chip of claim 39, wherein said first interconnecting structure comprises an electroplated metal.

45. The chip of claim 39, wherein said first interconnecting structure comprises a damascene metal.

46. The chip of claim 39, wherein said third interconnecting structure comprises copper.

47. The chip of claim 39, wherein said third interconnecting structure comprises gold.

48. The chip of claim 39 further comprising a third dielectric layer over said passivation layer, wherein said third dielectric layer comprises a portion on said top surface of said third interconnecting structure.

49. The chip of claim 48, wherein said third dielectric layer comprises a polymer.

50. The chip of claim 39 further comprising a third dielectric layer over said passivation layer, wherein said third dielectric layer comprises a portion between said third interconnecting structure and said passivation layer, wherein said third dielectric layer comprises a polymer.