Post passivation interconnection schemes on top of the IC chips
First Claim
Patent Images
1. A chip comprising:
- a silicon substrate;
a first dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said first dielectric layer;
a second interconnecting structure over said silicon substrate and in said first dielectric layer;
an insulating layer over said dielectric layer;
a third interconnecting structure over said insulating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a power is adapted to be provided to said third interconnecting structure, wherein said third interconnecting structure is provided by a topmost metal layer of interconnecting lines of said chip.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
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Citations
50 Claims
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1. A chip comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said first dielectric layer; a second interconnecting structure over said silicon substrate and in said first dielectric layer; an insulating layer over said dielectric layer; a third interconnecting structure over said insulating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a power is adapted to be provided to said third interconnecting structure, wherein said third interconnecting structure is provided by a topmost metal layer of interconnecting lines of said chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A chip comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said first dielectric layer; a second interconnecting structure over said silicon substrate and in said first dielectric layer; an insulating layer over said dielectric layer; and a third interconnecting structure over said insulating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a ground is adapted to be provided to said third interconnecting structure, wherein said third interconnecting structure is provided by a topmost metal layer of interconnecting lines of said chip. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A chip comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said first dielectric layer; a second interconnecting structure over said silicon substrate and in said first dielectric layer; a passivation layer over said first dielectric layer; and a third interconnecting structure over said passivation layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a power is adapted to be provided to said third interconnecting structure. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A chip comprising:
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a silicon substrate; a first dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said first dielectric layer; a second interconnecting structure over said silicon substrate and in said first dielectric layer; a passivation layer over said first dielectric layer; and a third interconnecting structure over said passivation layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said third interconnecting structure, wherein a top surface of said third interconnecting structure has no access for external connection, wherein a ground is adapted to be provided to said third interconnecting structure. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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Specification