Triaxial through-chip connection

• US 8,456,015 B2
• Filed: 01/06/2010
• Issued: 06/04/2013
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US12/683,027
• Publication Number:
  US 20100140776A1
• Time in Patent Office: 1,245 Days
• Field of Search: 438/675, 257/686, 257/774, 257/777, 257/E25.013, 257/E23.011
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06544 : Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.

Claims

1. An integrated circuit chip comprising:

a semiconductor;

a substrate located adjacent to the semiconductor;

an annular trench extending into the semiconductor and the substrate, wherein the annular trench includes an insulating material;

a first electrically conductive material bounding at least a portion of an outer surface of the insulating material;

a second electrically conductive material bounding at least a portion of an inner surface of the insulating material; and

a third electrically conductive material surrounded by the inner surface of the insulating material;

wherein the first, second, and third electrically conductive materials are electrically isolated from each other.

2. The integrated circuit chip of claim 1, further comprising a contact that extends outward from a surface of the semiconductor.

3. The integrated circuit chip of claim 2, wherein the contact comprises at least one of a rigid or malleable material configured for use in a post-and-penetration connection.

4. The integrated circuit chip of claim 2, wherein the contact is electrically connected to at least one of the first, second, or third electrically conductive materials.

5. The integrated circuit chip of claim 1, further comprising a dielectric material disposed on a wall of the annular trench.

6. The integrated circuit chip of claim 1, wherein at least one of the first, second, or third electrically conductive materials is grounded, and wherein the others of the first, second, or third electrically conductive materials are configured to communicate electrical signals.

7. The integrated circuit chip of claim 1, wherein the semiconductor is doped.

8. The integrated circuit chip of claim 1, wherein the first electrically conductive material is disposed on the at least a portion of the outer surface of the insulating material.

9. The integrated circuit chip of claim 1, wherein the second electrically conductive material is disposed on the at least a portion of the inner surface of the insulating material.

10. The integrated circuit chip of claim 1, further comprising an annulus of semiconductor material disposed between the second and third electrically conductive materials.

11. The integrated circuit chip of claim 1, wherein the insulating material comprises an annulus of insulating material, wherein the outer surface of the insulating material comprises an outer surface of the annulus of insulating material, and wherein the inner surface of the insulating material comprises an inner surface of the annulus of insulating material.

12. The integrated circuit chip of claim 1, wherein the first and second electrically conductive materials comprise a metallization deposited on the inner and outer surfaces of the insulating material.

13. An integrated circuit chip comprising:

a semiconductor material;

a via extending into the semiconductor material, wherein the via includes an annulus of insulating material;

a first electrically conductive material bounding at least a portion of an outer surface of the annulus of insulating material;

a second electrically conductive material bounding at least a portion of an inner surface of the annulus of insulating material; and

a third electrically conductive material within the annulus of insulating material;

wherein the first, second, and third electrically conductive materials are electrically isolated from each other.

14. The integrated circuit chip of claim 13, further comprising a contact that is electrically connected to the via and that extends away from an outer surface of the semiconductor material.

15. The integrated circuit chip of claim 14, wherein the contact comprises at least one of a rigid or malleable material configured for use in a post-and-penetration connection.

16. The integrated circuit chip of claim 14, wherein the contact is electrically connected to at least one of the first, second, or third electrically conductive materials.

17. The integrated circuit chip of claim 13, further comprising a dielectric material disposed on a wall of the via.

18. The integrated circuit chip of claim 13, wherein at least one of the first, second, or third electrically conductive materials is connected to an electrical ground, and wherein the others of the first, second, or third electrically conductive materials comprise electrical paths configured to communicate electrical signals.

19. The integrated circuit chip of claim 13, wherein the first electrically conductive material is disposed on the at least a portion of the outer surface of the annulus of insulating material.

20. The integrated circuit chip of claim 13, wherein the second electrically conductive material is disposed on the at least a portion of the inner surface of the annulus of insulating material.

21. The integrated circuit chip of claim 13, further comprising an annulus of semiconductor material disposed between the second and third electrically conductive materials.

22. The integrated circuit chip of claim 13, wherein the first and second electrically conductive materials comprise a metallization deposited on the inner and outer surfaces of the annulus of insulating material.

23. A stack of integrated circuit chips comprising:

a first chip, wherein the first chip includes;

a semiconductor;

a via extending into the semiconductor, wherein the via includes an annulus of insulating material;

a first electrically conductive material bounding at least a portion of an outer surface of the annulus of insulating material;

a second electrically conductive material bounding at least a portion of an inner surface of the annulus of insulating material; and

a third electrically conductive material within the annulus of insulating material;

wherein the first, second, and third electrically conductive materials are electrically isolated from each other; and

a second chip, wherein the second chip includes a first electrical contact that is electrically connected to at least one of the first, second, or third electrically conductive materials.

24. The stack of claim 23, wherein the first chip comprises a second electrical contact that is electrically connected to at least one of the first, second, or third electrically conductive materials.

25. The stack of claim 23, wherein the second electrical contact comprises one of a rigid material or a malleable material, and wherein the first electrical contact comprises the other of the rigid material or the malleable material.

26. The stack of claim 25, wherein the first and second electrical contacts are physically and electrically connected.

27. The stack of claim 25, wherein the rigid material and the malleable material form a post-and-penetration connection between the first chip and the second chip.

28. The stack of claim 23, wherein the first electrically conductive material is disposed on the at least a portion of the outer surface of the annulus of insulating material.

29. The stack of claim 23, wherein the second electrically conductive material is disposed on the at least a portion of the inner surface of the annulus of insulating material.

30. The stack of claim 23, further comprising an annulus of semiconductor material disposed between the second and third electrically conductive materials.

31. The stack of claim 23, wherein the first and second electrically conductive materials comprise a metallization deposited on the inner and outer surfaces of the annulus of insulating material.

32. An electronic device comprising a chip, wherein the chip includes a doped semiconductor and a substrate and is processed by a method comprising:

etching a via trench between an outer surface of the doped semiconductor and the substrate, wherein a first portion of the via trench is bounded by the doped semiconductor and a second portion of the via trench is bounded by the substrate;

coating at least a portion of an outer wall of the via trench with a first electrically conductive material;

coating at least a portion of an inner wall of the via trench with a second electrically conductive material;

introducing a third electrically conductive material in the via trench to form an electrically conductive path between the doped semiconductor and the substrate; and

thinning a surface of the substrate to expose the first, second, and third electrically conductive materials, wherein the first, second, and third electrically conductive materials are electrically isolated from each other.

33. The electronic device of claim 32, wherein the chip is further processed by filling a void between the first and second electrically conductive materials with an electrically insulating material.

34. The electronic device of claim 32, wherein the chip is further processed by coating the first and second electrically conductive materials with an electrically insulating material.

35. The electronic device of claim 32, wherein the chip is further processed by applying a dielectric material to the inner and outer walls of the via trench.

36. The electronic device of claim 35, wherein the chip is further processed by removing a portion of semiconductor material bounded by the via trench.

37. The electronic device of claim 32, wherein the chip is further processed by forming a contact from rigid material disposed on a portion of semiconductor material bounded by the via trench, and wherein the rigid material is electrically connected to at least one of the first, second, or third electrically conductive materials.