Lock detector and method of detecting lock status for phase lock loop

• US 8,456,207 B1
• Filed: 11/16/2011
• Issued: 06/04/2013
• Est. Priority Date: 11/16/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Feng Wei, Chen, Yen-Jen, Jou, Chewn-Pu, Yen, Kyle, Chen, Huan-Neng
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/297,658
• Publication Number:
  US 20130120035A1
• Time in Patent Office: 566 Days
• Field of Search: 327/147, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

Claims

1. A lock detector for a Phase Lock Loop (PLL) circuit comprising:

a first signal counting circuit configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value;

a second signal counting circuit configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, the second oscillating signal being generated in relation to the first oscillating signal;

a comparator configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value; and

a lock status unit configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.

2. The lock detector of claim 1, wherein the predetermined cycle value is 4, 8, 16, or 20.

3. The lock detector of claim 1, wherein the predetermined number is 10.

4. The lock detector of claim 1, wherein each of the observation periods is defined by a count of the occurrence of a rising or a falling edge of the first oscillating signal and a determination that a counted number of the occurrence of a rising or a falling edge of the first oscillating signal is equal to or greater than the predetermined cycle value.

5. The lock detector of claim 4, wherein the first signal counting circuit comprises a counter and a maximum detector connected to the counter, and the counter is configured to:

generate the counted number of the occurrence of a rising or a falling edge of the first oscillating signal; and

overflow after the counted number is equal to the predetermined cycle value.

6. The lock detector of claim 5, wherein the second signal counting circuit is configured to be reset by the first signal counting circuit in response to the overflow of the counter of the first signal counting circuit.

7. The lock detector of claim 4, wherein the second signal counting circuit is configured to be reset by the comparator after the counted number of the occurrence of a rising or a falling edge of the first oscillating signal is equal to or greater than the predetermined cycle value.

8. A lock detector for a Phase Lock Loop (PLL) circuit comprising:

a lock signal generator configured to generate a lock signal according to a relationship between a first maximum value and a second maximum value;

a first counter configured to generate a counter value in response to a first oscillating signal;

a first maximum detector coupled between the first counter and the lock signal generator and configured to determine the first maximum value of the counter value from the first counter;

a second counter configured to generate a counter value in response to a second oscillating signal generated in relation to the first oscillating signal; and

a second maximum detector coupled between the second counter and the lock signal generator and configured to determine the second maximum value of the counter value from the second counter.

9. The lock detector of claim 8, wherein the lock signal generator comprises:

a comparator configured to generate an equal event or an unequal event by comparing the first maximum value and the second maximum value.

10. The lock detector of claim 9, wherein the lock signal generator further comprises:

a third counter configured to generate an equal event counter value in response to the equal event from the comparator; and

a lock status unit configured to generate the lock signal after the equal event counter value from the third counter equals a predetermined counter threshold value.

11. The lock detector of claim 10, wherein the third counter is configured to be reset after the generation of the lock signal or the generation of the unequal event.

12. The lock detector of claim 10, wherein the predetermined threshold counter value is 10.

13. The lock detector of claim 8, wherein the first and second counters are configured to be reset after the counter value of the first counter is equal to a predetermined cycle value.

14. The lock detector of claim 13, wherein the first counter is configured to overflow after the counter value of the first counter is equal to the predetermined cycle value, and the second counter is reset in response to an occurrence of overflow of the first counter.

15. The lock detector of claim 13, wherein the predetermined cycle value is 4, 8, 16, or 20.

16. A method of detecting a lock status of a Phase Lock Loop (PLL) circuit, the method comprising:

generating a first maximum value by performing a counting operation based on a first oscillating signal;

generating a second maximum value by performing a counting operation based on a second oscillating signal generated by the PLL circuit relative to the first oscillating signal;

generating an equal event or an unequal event by comparing the first maximum value and the second maximum value;

generating an equal event counter value, by a counter, in response to the equal event; and

generating a lock signal after the equal event counter value equals a predetermined counter threshold value.

17. The method of claim 16, further comprising:

resetting the first and second maximum values after the first maximum value equals a predetermined cycle value.

18. The method of claim 17, wherein the predetermined cycle value is 4, 8, 16, or 20.

19. The method of claim 16, wherein the predetermined threshold counter value is 10.

20. The method of claim 16, further comprising:

resetting the equal event counter value after the generation of the lock signal or the generation of the unequal event.