Liquid crystal display device

• US 8,456,396 B2
• Filed: 12/23/2010
• Issued: 06/04/2013
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi
• Primary Examiner(s): DINH, DUC Q
• Application Number:
  US12/977,556
• Publication Number:
  US 20110187694A1
• Time in Patent Office: 894 Days
• Field of Search: 345/87, 345/89, 345/98, 345/99, 345/100, 345/690, 345/204, 345/211
• US Class Current: 345/87
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133622 Colour sequential illumination
• CPC Class Codes: G02F 1/133753 with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/1393 the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells G02F1/1396, G02F1/141 take precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2310/024 Scrolling of light from the illumination source over the display in combination with the scanning of the display screen
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/342 using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3685 : Details of drivers for data electrodes
• CPC Class Codes: G11C 19/28 : using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 21/67167 : surrounding a central transfer chamber
• CPC Class Codes: H01L 27/06 : including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/1222 : with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 : with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 : with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 : integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/15 : including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 27/156 : two-dimensional arrays
• CPC Class Codes: H01L 29/247 : Amorphous materials
• CPC Class Codes: H01L 29/78693 : the semiconducting oxide being amorphous
• CPC Class Codes: H10K 2102/3023 : Direction of light emission
• CPC Class Codes: H10K 2102/3026 : Top emission
• CPC Class Codes: H10K 2102/3031 : Two-side emission, e.g. transparent OLEDs [TOLED]
• CPC Class Codes: H10K 50/8426 : Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 : the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 : Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 : Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/35 : comprising red-green-blue [RGB] subpixels
• CPC Class Codes: H10K 59/351 : comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
• CPC Class Codes: H10K 59/352 : the areas of the RGB subpixels being different
• CPC Class Codes: H10K 59/8722 : Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 71/00 : Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/421 : using coherent electromagnetic radiation, e.g. laser annealing

Abstract

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

Claims

1. A semiconductor device comprising:

a first driver circuit including first to sixth transistors; and

first to fifth wirings,

wherein;

a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a gate terminal of the second transistor, and a gate terminal of the first transistor is electrically connected to the first wiring;

a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to the fifth wiring;

a first terminal of the third transistor is electrically connected to the second wiring, a second terminal of the third transistor is electrically connected to the gate terminal of the second transistor, and a gate terminal of the third transistor is electrically connected to the fourth wiring;

a first terminal of the fourth transistor is electrically connected to the second wiring, a second terminal of the fourth transistor is electrically connected to the fifth wiring, and a gate terminal of the fourth transistor is electrically connected to the fourth wiring;

a first terminal of the fifth transistor is electrically connected to the second wiring, a second terminal of the fifth transistor is electrically connected to the fifth wiring, and a gate terminal of the fifth transistor is electrically connected to a first terminal of the sixth transistor; and

a second terminal of the sixth transistor is electrically connected to the third wiring.

2. The semiconductor device according to claim 1 further comprising;

a first pixel electrically connected to the first driver circuit through the first wiring; and

a second pixel electrically connected to the first driver circuit through the fifth wiring.

3. The semiconductor device according to claim 1, wherein each of the first to fourth transistors is an N-channel transistor.

4. The semiconductor device according to claim 1, wherein each of the first to fourth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

5. The semiconductor device according to claim 1, further comprising a capacitor between the second terminal and the gate terminal of the first transistor.

6. The semiconductor device according to claim 1 further comprising:

a second driver circuit including at least seventh to tenth transistors; and

sixth to eleventh wirings,

wherein;

a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to a gate terminal of the eight transistor, and a gate terminal of the seventh transistor is electrically connected to the tenth wiring;

a first terminal of the eighth transistor is electrically connected to the eighth wiring, and a second terminal of the eighth transistor is electrically connected to the eleventh wiring;

a first terminal of the ninth transistor is electrically connected to the seventh wiring, a second terminal of the ninth transistor is electrically connected to the gate terminal of the eighth transistor, and a gate terminal of the ninth transistor is electrically connected to the ninth wiring; and

a first terminal of the tenth transistor is electrically connected to the seventh wiring, a second terminal of the tenth transistor is electrically connected to the eleventh wiring, and a gate terminal of the tenth transistor is electrically connected to the ninth wiring.

7. The semiconductor device according to claim 6 further comprising;

a first pixel electrically connected to the first driver circuit through the first wiring;

a second pixel electrically connected to the first driver circuit through the fifth wiring;

a third pixel electrically connected to the second driver circuit through the tenth wiring; and

a fourth pixel electrically connected to the second driver circuit through the eleventh wiring.

8. The semiconductor device according to claim 6, wherein each of the first to eighth transistors is an N-channel transistor.

9. The semiconductor device according to claim 6,

wherein each of the first to eighth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

10. The semiconductor device according to claim 6 further comprising:

a first capacitor between the second terminal and the gate terminal of the first transistor; and

a second capacitor between the second terminal and the gate terminal of the seventh transistor.

11. A train incorporated with the semiconductor device according to claim 1, wherein the semiconductor device is applied to at least one of a door, a window, and a sealing of the train.

12. A car incorporated with the semiconductor device according to claim 1, wherein the semiconductor device is applied to at least one of a body and a door of the car.

13. An airplane incorporated with the semiconductor device according to claim 1, wherein the semiconductor device is applied to at least one of a sealing, a seat, and a door in the airplane.

14. A column-shaped object incorporated with the semiconductor device according to claim 1, wherein the semiconductor device is provided on a curved surface of the column-shaped object.

15. A constructed object incorporated with the semiconductor device according to claim 1, wherein the semiconductor device is incorporated into a side wall of the constructed object.

16. A television device incorporated with the semiconductor device according to claim 1, wherein the television device is a wall-hanging type.

17. A semiconductor device comprising:

a first driver circuit including first to seventh transistors; and

first to fifth wirings,

wherein;

a first terminal of the first transistor is electrically connected to the fifth wiring, a second terminal of the first transistor is electrically connected to a gate terminal of the second transistor, and a gate terminal of the first transistor is electrically connected to the fifth wiring;

a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to the first wiring;

a first terminal of the third transistor is electrically connected to the gate terminal of the second transistor, a second terminal of the third transistor is electrically connected to the second wiring, and a gate terminal of the third transistor is electrically connected to the fourth wiring;

a first terminal of the fourth transistor is electrically connected to the first wiring, a second terminal of the fourth transistor is electrically connected to the second wiring, and a gate terminal of the fourth transistor is electrically connected to the fourth wiring;

a first terminal of the fifth transistor is electrically connected to the second wiring, a second terminal of the fifth transistor is electrically connected to the fifth wiring, and a gate terminal of the fifth transistor is electrically connected to a first terminal of the sixth transistor; and

a second terminal of the sixth transistor is electrically connected to the third wiring, and a gate terminal of the sixth transistor is electrically connected to a first terminal of the seventh transistor.

18. The semiconductor device according to claim 17 further comprising;

a first pixel electrically connected to the first driver circuit through the fifth wiring; and

a second pixel electrically connected to the first driver circuit through the first wiring.

19. The semiconductor device according to claim 17, wherein each of the first to fourth transistors is an N-channel transistor.

20. The semiconductor device according to claim 17, wherein each of the first to fourth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

21. The semiconductor device according to claim 17, further comprising a capacitor between the second terminal and the gate terminal of the first transistor.

22. The semiconductor device according to claim 17 further comprising:

a second driver circuit including eighth to eleventh transistors; and

sixth to tenth wiring,

wherein;

a first terminal of the eighth transistor is electrically connected to the tenth wiring, a second terminal of the eighth transistor is electrically connected to a gate terminal of the ninth transistor, and a gate terminal of the eighth transistor is electrically connected to the tenth wiring;

a first terminal of the ninth transistor is electrically connected to the eighth wiring, and a second terminal of the ninth transistor is electrically connected to the sixth wiring;

a first terminal of the tenth transistor is electrically connected to the gate terminal of the ninth transistor, a second terminal of the tenth transistor is electrically connected to the seventh wiring, and a gate terminal of the tenth transistor is electrically connected to the ninth wiring; and

a first terminal of the eleventh transistor is electrically connected to the sixth wiring, a second terminal of the eleventh transistor is electrically connected to the seventh wiring, and a gate terminal of the eleventh transistor is electrically connected to the ninth wiring.

23. The semiconductor device according to claim 22 further comprising;

a first pixel electrically connected to the first driver circuit through the fifth wiring;

a second pixel electrically connected to the first driver circuit through the first wiring;

a third pixel electrically connected to the second driver circuit through the tenth wiring; and

a fourth pixel electrically connected to the second driver circuit through the sixth wiring.

24. The semiconductor device according to claim 22,

wherein the first wiring and the sixth wiring are electrically connected to each other;

and

the fifth wiring and the tenth wiring are electrically connected to each other.

25. The semiconductor device according to claim 22,

wherein the second wiring and the seventh wiring are electrically connected to each other;

the third wiring and the eighth wiring are electrically connected to each other; and

the fourth wiring and the ninth wiring are electrically connected to each other.

26. The semiconductor device according to claim 22, wherein each of the first to eighth transistors is an N-channel transistor.

27. The semiconductor device according to claim 22,

wherein each of the first to eighth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

28. The semiconductor device according to claim 22 further comprising:

a first capacitor between the second terminal and the gate terminal of the first transistor; and

a second capacitor between the second terminal and the gate terminal of the fifth transistor.

29. A train incorporated with the semiconductor device according to claim 17, wherein the semiconductor device is applied to at least one of a door, a window, and a sealing of the train.

30. A car incorporated with the semiconductor device according to claim 17, wherein the semiconductor device is applied to at least one of a body and a door of the car.

31. An airplane incorporated with the semiconductor device according to claim 17, wherein the semiconductor device is applied to at least one of a sealing, a seat, and a door in the airplane.

32. A column-shaped object incorporated with the semiconductor device according to claim 17, wherein the semiconductor device is provided on a curved surface of the column-shaped object.

33. A constructed object incorporated with the semiconductor device according to claim 17, wherein the semiconductor device is incorporated into a side wall of the constructed object.

34. A television device incorporated with the semiconductor device according to claim 17, wherein the television device is a wall-hanging type.

71. The semiconductor device according to claim 17, further comprising a twelfth wiring electrically connected to a second terminal and a gate terminal of the seventh transistor.

35. A semiconductor device comprising:

a first driver circuit including at least first to fifth transistors; and

first to seventh wirings,

wherein;

a first terminal of the first transistor is electrically connected to the first wiring,

a second terminal of the first transistor is electrically connected to a gate terminal of the second transistor, and a gate terminal of the first transistor is electrically connected to the fifth wiring;

a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to the sixth wiring;

a first terminal of the third transistor is electrically connected to the gate terminal of the second transistor, a second terminal of the third transistor is electrically connected to the second wiring, and a gate terminal of the third transistor is electrically connected to the fourth wiring;

a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the second wiring, and a gate terminal of the fourth transistor is electrically connected to the fourth wiring;

a first terminal of the fifth transistor is electrically connected to the sixth wiring, a second terminal of the fifth transistor is electrically connected to the second wiring, and a gate terminal of the fifth transistor is electrically connected to the seventh wiring; and

at least one of the first to fifth transistors comprises a semiconductor layer which includes a metal oxide, the metal oxide including an indium.

36. The semiconductor device according to claim 35 further comprising;

a first pixel electrically connected to the first driver circuit through the fifth wiring; and

a second pixel is electrically connected to the first driver circuit through the sixth wiring.

37. The semiconductor device according to claim 35, wherein each of the first to fifth transistors is an N-channel transistor.

38. The semiconductor device according to claim 35, wherein each of the first to fifth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

39. The semiconductor device according to claim 35 further comprising a capacitor between the second terminal and the gate terminal of the first transistor.

40. The semiconductor device according to claim 35 further comprising:

a second driver circuit including at least sixth to tenth transistors; and

eighth to fourteenth wirings,

wherein;

a first terminal of the sixth transistor is electrically connected to the eighth wiring, a second terminal of the sixth transistor is electrically connected to a gate terminal of the seventh transistor, and a gate terminal of the sixth transistor is electrically connected to the twelfth wiring;

a first terminal of the seventh transistor is electrically connected to the tenth wiring, and a second terminal of the seventh transistor is electrically connected to the thirteenth wiring;

a first terminal of the eighth transistor is electrically connected to the ninth wiring, a second terminal of the eighth transistor is electrically connected to the gate terminal of the seventh transistor, and a gate terminal of the eighth transistor is electrically connected to the eleventh wiring;

a first terminal of the ninth transistor is electrically connected to the thirteenth wiring, a second terminal of the ninth transistor is electrically connected to the ninth wiring, and a gate terminal of the ninth transistor is electrically connected to the eleventh wiring; and

a first terminal of the tenth transistor is electrically connected to the thirteenth wiring, a second terminal of the tenth transistor is electrically connected to the ninth wiring, and a gate terminal of the tenth transistor is electrically connected to the fourteenth wiring.

41. The semiconductor device according to claim 40, further comprising:

a first pixel electrically connected to the first driver circuit through the fifth wiring;

a second pixel electrically connected to the first driver circuit through the sixth wiring;

a third pixel electrically connected to the second driver circuit through the twelfth wiring; and

a fourth pixel electrically connected to the second driver circuit through the thirteenth wiring.

42. The semiconductor device according to claim 40,

wherein the fifth wiring and the twelfth wiring are electrically connected to each other;

and the sixth wiring and the thirteenth wiring are electrically connected to each other.

43. The semiconductor device according to claim 40,

wherein the first wiring and the eighth wiring are electrically connected to each other;

the second wiring and the ninth wiring are electrically connected to each other;

the third wiring and the tenth wiring are electrically connected to each other;

the fourth wiring and the eleventh wiring are electrically connected to each other; and

the seventh wiring and the fourteenth wiring are electrically connected to each other.

44. The semiconductor device according to claim 40, wherein each of the first to tenth transistors is an N-channel transistor.

45. The semiconductor device according to claim 40, wherein each of the first to tenth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

46. The semiconductor device according to claim 40 further comprising:

a first capacitor between the second terminal and the gate terminal of the first transistor; and

a second capacitor between the second terminal and the gate terminal of the sixth transistor.

47. A train incorporated with the semiconductor device according to claim 35, wherein the semiconductor device is applied to at least one of a door, a window, and a sealing of the train.

48. A car incorporated with the semiconductor device according to claim 35, wherein the semiconductor device is applied to at least one of a body and a door of the car.

49. An airplane incorporated with the semiconductor device according to claim 35, wherein the semiconductor device is applied to at least one of a sealing, a seat, and a door in the airplane.

50. A column-shaped object incorporated with the semiconductor device according to claim 35, wherein the semiconductor device is provided on a curved surface of the column-shaped object.

51. A constructed object incorporated with the semiconductor device according to claim 35, wherein the semiconductor device is incorporated into a side wall of the constructed object.

52. A television device incorporated with the semiconductor device according to claim 35, wherein the television device is a wall-hanging type.

53. A semiconductor device comprising:

a first driver circuit including at least first to fifth transistors; and

first to sixth wirings,

wherein;

a first terminal of the first transistor is electrically connected to the fifth wiring,

a second terminal of the first transistor is electrically connected to a gate terminal of the second transistor, and a gate terminal of the first transistor is electrically connected to the fifth wiring;

a first terminal of the second transistor is electrically connected to the third wiring, and a second terminal of the second transistor is electrically connected to the sixth wiring;

a first terminal of the third transistor is electrically connected to the second wiring, a second terminal of the third transistor is electrically connected to the gate terminal of the second transistor, and a gate terminal of the third transistor is electrically connected to the fourth wiring;

a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the second wiring, and a gate terminal of the fourth transistor is electrically connected to the fourth wiring;

a first terminal of the fifth transistor is electrically connected to the sixth wiring, a second terminal of the fifth transistor is electrically connected to the second wiring, and a gate terminal of the fifth transistor is electrically connected to the first wiring; and

at least one of the first to fifth transistors comprises a semiconductor layer which includes a metal oxide, the metal oxide including an indium.

54. The semiconductor device according to claim 53 further comprising;

a first pixel electrically connected to the first driver circuit through the fifth wiring; and

a second pixel electrically connected to the first driver circuit through the sixth wiring.

55. The semiconductor device according to claim 53, wherein each of the first to fifth transistors is an N-channel transistor.

56. The semiconductor device according to claim 53,

wherein each of the first to fifth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

57. The semiconductor device according to claim 53 further comprising a capacitor between the second terminal and the gate terminal of the first transistor.

58. The semiconductor device according to claim 53 further comprising:

a second driver circuit including at least sixth to tenth transistors; and

seventh to twelfth wirings,

wherein;

a first terminal of the sixth transistor is electrically connected to the eleventh wiring, a second terminal of the sixth transistor is electrically connected to a gate terminal of the seventh transistor, and a gate terminal of the sixth transistor is electrically connected to the eleventh wiring;

a first terminal of the seventh transistor is electrically connected to the ninth wiring, and a second terminal of the seventh transistor is electrically connected to the twelfth wiring;

a first terminal of the eighth transistor is electrically connected to the eighth wiring, a second terminal of the eighth transistor is electrically connected to the gate terminal of the seventh transistor, and a gate terminal of the eighth transistor is electrically connected to the tenth wiring;

a first terminal of the ninth transistor is electrically connected to the eighth wiring, a second terminal of the ninth transistor is electrically connected to the twelfth wiring, and a gate terminal of the ninth transistor is electrically connected to the tenth wiring; and

a first terminal of the tenth transistor is electrically connected to the eighth wiring, a second terminal of the tenth transistor is electrically connected to the twelfth wiring, and a gate terminal of the tenth transistor is electrically connected to the seventh wiring.

59. The semiconductor device according to claim 58, further comprising:

a first pixel electrically connected to the first driver circuit through the fifth wiring;

a second pixel electrically connected to the first driver circuit through the sixth wiring;

a third pixel electrically connected to the second driver circuit through the eleventh wiring; and

a fourth pixel electrically connected to the second driver circuit through the twelfth wiring.

60. The semiconductor device according to claim 58,

wherein the fifth wiring and the eleventh wiring are electrically connected to each other;

and the sixth wiring and the twelfth wiring are electrically connected to each other.

61. The semiconductor device according to claim 58,

wherein the first wiring and the seventh wiring are electrically connected to each other;

the second wiring and the eighth wiring are electrically connected to each other;

the third wiring and the ninth wiring are electrically connected to each other; and

the fourth wiring and the tenth wiring are electrically connected to each other.

62. The semiconductor device according to claim 58, wherein each of the first to tenth transistors is an N-channel transistor.

63. The semiconductor device according to claim 58, wherein each of the first to tenth transistors includes a semiconductor layer comprising one of zinc oxide and indium gallium zinc oxide.

64. The semiconductor device according to claim 58 further comprising:

a first capacitor between the second terminal and the gate terminal of the first transistor; and

a second capacitor between the second terminal and the gate terminal of the sixth transistor.

65. A train incorporated with the semiconductor device according to claim 53, wherein the semiconductor device is applied to at least one of a door, a window, and a sealing of the train.

66. A car incorporated with the semiconductor device according to claim 53, wherein the semiconductor device is applied to at least one of a body and a door of the car.

67. An airplane incorporated with the semiconductor device according to claim 53, wherein the semiconductor device is applied to at least one of a sealing, a seat, and a door in the airplane.

68. A column-shaped object incorporated with the semiconductor device according to claim 53, wherein the semiconductor device is provided on a curved surface of the column-shaped object.

69. A constructed object incorporated with the semiconductor device according to claim 53, wherein the semiconductor device is incorporated into a side wall of the constructed object.

70. A television device incorporated with the semiconductor device according to claim 53, wherein the television device is a wall-hanging type.