Method of spin torque MRAM process integration

• US 8,456,883 B1
• Filed: 05/29/2012
• Issued: 06/04/2013
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Headway Technologies Incorporated (TDK Corporation)
• Inventors: Liu, Daniel
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US13/482,157
• Time in Patent Office: 371 Days
• Field of Search: 438/3, 438/200, 257/369, 257/E21.627, 257/E21.665, 257/E27.108, 365/66, 365/158, 365/171
• US Class Current: 365/66
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.

Claims

1. A method of fabricating a magnetic random access memory device comprising:

providing CMOS devices in a substrate having a topmost metal layer wherein said topmost metal layer comprises metal landing pads and metal connecting pads;

providing a plurality of magnetic tunnel junction (MTJ) structures over said CMOS devices and connected to said metal landing pads;

covering said MTJ structures with a first dielectric layer and polishing said first dielectric layer until said MTJ structures are exposed;

etching openings in said first dielectric layer to said metal connecting pads;

filling said openings with a copper layer;

etching back said copper layer to leave said copper layer only within said openings;

thereafter, depositing an aluminum layer over said first dielectric layer contacting said copper layer and said MTJ structures; and

patterning said aluminum layer to form a bit line.

2. The method according to claim 1 wherein said magnetic random access memory device comprises an in-plane or out-of-plane spin-torque-transfer random access memory device, a spin value read head or sensor, or other spintronic device.

3. The method according to claim 1 further comprising:

depositing a second dielectric layer over said metal contact pads and said metal connecting pads;

etching via openings through said second dielectric layer to said metal contact pads;

filling said via openings with a via copper layer; and

polishing said via copper layer to said second dielectric layer leaving said via copper layer only in said via openings to form copper via connections.

4. The method according to claim 3 further comprising:

depositing a metal layer over said copper via connections and said second dielectric layer;

patterning said metal layer to form metal separation pads over said copper via connections; and

forming said MTJ structures on said metal separation pads wherein said MTJ structures are connected to said metal landing pads through said metal separation pads and said copper via connections.

5. The method according to claim 1, wherein said etching openings in said first dielectric layer to said metal connecting pads further comprises over etching said first dielectric layer until said metal connecting pads are exposed within said openings.

6. The method according to claim 1 wherein said filling said openings with a copper layer comprises:

depositing a seed layer over said first dielectric layer and on inside walls and bottom of said openings; and

plating a copper layer on said seed layer until said copper layer fills said openings.

7. The method according to claim 1 wherein said copper layer is plated to a thickness of between about 0.28 and 0.5 microns.

8. The method according to claim 1 wherein said etching back of said copper layer comprises a wet etch chemistry.

9. The method according to claim 1 wherein said aluminum layer has a thickness of between about 4000 and 8000 Angstroms.

10. A method of fabricating a spin torque-transfer magnetic random access memory device comprising:

providing CMOS devices in a substrate having a topmost metal layer wherein said topmost metal layer comprises metal landing pads and metal connecting pads;

depositing a first dielectric layer over said metal contact pads and said metal connecting pads;

etching via openings through said dielectric layer to said metal contact pads;

filling said via openings with a via copper layer;

polishing said via copper layer to said first dielectric layer leaving said via copper layer only in said via openings to form copper via connections;

depositing a metal layer over said copper via connections and said first dielectric layer;

patterning said metal layer to form metal separation pads over said copper via connections;

forming a plurality of magnetic tunnel junction (MTJ) structures on said metal separation pads wherein said MTJ structures are connected to said metal landing pads through said metal separation pads and said copper via connections;

covering said MTJ structures with a second dielectric layer and polishing said second dielectric layer until said MTJ structures are exposed;

etching openings in said second dielectric layer to said metal connecting pads;

depositing a seed layer over said second dielectric layer and on inside walls and bottom of said openings;

plating a copper layer on said seed layer until said copper layer fills said openings;

etching back said copper layer and removing said seed layer not covered by said copper layer;

thereafter, depositing an aluminum layer over said second dielectric layer contacting said copper layer and said MTJ structures; and

patterning said aluminum layer to form a bit line.

11. The method according to claim 10 wherein said spin-torque-transfer random access memory device comprises an in-plane or out-of-plane spin-torque-transfer random access memory device, a spin value read head or sensor, or other spintronic device.

12. The method according to claim 10, wherein said etching openings in said second dielectric layer to said metal connecting pads further comprises over etching said second dielectric layer until said metal connecting pads are exposed within said openings.

13. The method according to claim 10 wherein said seed layer comprises tantalum having a thickness of between about 100 and 300 Angstroms.

14. The method according to claim 10 wherein said copper layer is plated to a thickness of between about 0.28 and 0.5 microns.

15. The method according to claim 10 wherein said etching back of said copper layer comprises a wet etch chemistry.

16. The method according to claim 10 wherein said aluminum layer has a thickness of between about 4000 and 8000 Angstroms.

17. A spin-torque-transfer magnetic random access memory device comprising:

CMOS devices in a substrate having a topmost metal layer wherein said topmost metal layer comprises metal landing pads and metal connecting pads;

a plurality of magnetic tunnel junction (MTJ) structures over said CMOS devices and connected to said metal landing pads; and

an aluminum bit line contacting said MTJ structures and contacting copper connections extending downward through a dielectric layer to said metal connecting pads.

18. The device according to claim 17 wherein said spin-torque-transfer random access memory device comprises an in-plane or out-of-plane spin-torque-transfer random access memory device, a spin value read head or sensor, or other spintronic device.

19. The device according to claim 17 further comprising:

copper via connections on said metal landing pads; and

metal separation pads on said copper via connections wherein said MTJ structures are formed on said metal separation pads and wherein said MTJ structures are connected to said metal landing pads through said metal separation pads and said copper via connections.

20. The device according to claim 17 further comprising a tantalum barrier layer surrounding said copper connections.