Non-volatile memory unit cell with improved sensing margin and reliability

• US 8,456,916 B2
• Filed: 07/04/2012
• Issued: 06/04/2013
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Hsin-Ming, Wang, Shih-Chen, Ching, Wen-Hao, Lai, Yen-Hsin, Lu, Hau-Yan, Yang, Ching-Sung
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HOANG, TRI M
• Application Number:
  US13/541,755
• Publication Number:
  US 20120273860A1
• Time in Patent Office: 335 Days
• Field of Search: 365/185.18, 365/185.05, 365/185.09
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

Claims

1. An only-one-polysilicon layer non-volatile memory unit cell comprising:

a first P-type transistor having a gate and a first source/drain;

a second P-type transistor having a gate and a first source/drain;

a N-type transistor pair having a third transistor and a fourth transistor that are connected, the third transistor and the fourth transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated;

a first coupling capacitor, one end of the first coupling capacitor being connected to the gate of the first transistor and coupled to the first floating polysilicon gate, the other end of the first coupling capacitor receiving a first control voltage; and

a second coupling capacitor, one end of the second coupling capacitor being connected to the gate of the second transistor and coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receiving a second control voltage,

wherein the N-type transistor pair is connected to a switch transistor, when the switch transistor is turned on according to a word line signal, data stored in the only-one-polysilicon layer non-volatile memory unit cell are read out.

2. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the first transistor further has a second source/drain, the second transistor also has a second source/drain and the second source/drain of the first transistor is coupled to the second source/drain of the second transistor.

3. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the salicide protection layer are added on top of the floating polysilicon gate layers for charge retention improvement.

4. The only-one-polysilicon layer non-volatile memory unit cell according to claim 3, wherein the third and fourth transistors are N-type native transistors or receiving additional lightly doped drain (LDD) implantation to reduce the threshold voltages.

5. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the first and second coupling capacitors are constructed in a P-well of a deep N-well.