Memory write error correction circuit

• US 8,456,926 B2
• Filed: 01/25/2011
• Issued: 06/04/2013
• Est. Priority Date: 11/18/2010
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Group)
• Original Assignee: Grandis, Inc. (Samsung Group)
• Inventors: Ong, Adrian E., Nitikin, Vladimir
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/013,616
• Publication Number:
  US 20120127804A1
• Time in Patent Office: 861 Days
• Field of Search: 365/49.1, 365/49.17, 365/158, 365/185.09, 365/185.33, 365/189.05, 365/189.07, 365/200, 365/230.08, 365/230.06
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.

Claims

1. A memory circuit comprising:

a compare block configured to compare a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell, said compare block further configured to store an address of the memory cell in which the second data is stored if the second data does not match the first data, said memory cell being written to during subsequent write cycles after the second data does not match the first data.

2. The memory circuit of claim 1 wherein said address is stored in a tag memory.

3. The memory circuit of claim 1 further comprising:

a memory array;

a write block coupled between the memory array and the compare block; and

a read block coupled between the memory array and the compare block wherein the read block is adapted to sense the second data.

4. The memory circuit of claim 1 further comprising a control logic configured to store an inverse of the second data to the memory cell when the memory cell is not being accessed for a normal write operation by a device external to the memory.

5. The memory circuit of claim 1 wherein said memory cell is a DRAM, SRAM, ROM, PROM, EEPROM, FLASH, FeRAM, PRAM, MRAM or STT-MRAM cell.

6. The memory system of claim 3 wherein said memory array comprises at least one column coupled to a plurality of said memory cells wherein said column comprises a first signal line and a second signal line, and said memory cell comprises a first current carrying terminal coupled to said first signal line, a second current carrying terminal coupled to said second signal line and a control terminal coupled to a word-line.

7. The memory circuit of claim 6 wherein said memory cell further comprises:

a magnetic tunnel junction having a first terminal coupled to said first current carrying terminal of said memory cell; and

a first transistor having a first current carrying terminal coupled to said second current carrying terminal of said non-volatile memory cell, a gate terminal coupled to said control terminal of said non-volatile memory cell and a second current carrying terminal coupled to a second terminal of said magnetic tunnel junction.

8. A method of correcting write errors during a write operation in a memory circuit, the method comprising:

comparing a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell during a write operation;

storing an address of the memory cell in which the second data is stored if the second data does not match the first data; and

writing to said memory cell during subsequent write cycles to correct said write error.

9. The method of claim 8 further comprising:

latching the address of the memory cell;

latching the first data;

writing the first data into a memory array at the address of the memory cell; and

sensing the second data during the write operation.

10. A method of correcting write errors during a write operation in a memory circuit, the method comprising:

comparing a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell during a write operation;

inverting said second data if the second data does not match the first data; and

writing said inverted second data to an address of the memory cell in which the second data is stored if the second data does not match the first data to correct said write error.

11. The method of claim 10 further comprising:

latching the address of the memory cell;

latching the first data;

writing the first data into a memory array at the address of the memory cell; and

sensing the second data during the write operation.

12. A method of correcting write errors after a write operation in a memory circuit, the method comprising:

loading an address of a memory cell in which a second data is stored if the second data does not match a first data after a write operation;

sensing the second data;

inverting said second data; and

writing said inverted second data to an address of the memory cell in which the second data is stored to correct said write error.