Memory write error correction circuit
First Claim
1. A memory circuit comprising:
- a compare block configured to compare a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell, said compare block further configured to store an address of the memory cell in which the second data is stored if the second data does not match the first data, said memory cell being written to during subsequent write cycles after the second data does not match the first data.
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Accused Products
Abstract
Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation.
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Citations
12 Claims
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1. A memory circuit comprising:
a compare block configured to compare a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell, said compare block further configured to store an address of the memory cell in which the second data is stored if the second data does not match the first data, said memory cell being written to during subsequent write cycles after the second data does not match the first data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of correcting write errors during a write operation in a memory circuit, the method comprising:
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comparing a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell during a write operation; storing an address of the memory cell in which the second data is stored if the second data does not match the first data; and writing to said memory cell during subsequent write cycles to correct said write error. - View Dependent Claims (9)
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10. A method of correcting write errors during a write operation in a memory circuit, the method comprising:
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comparing a first data adapted to be stored in a memory cell to a second data previously stored in the memory cell during a write operation; inverting said second data if the second data does not match the first data; and writing said inverted second data to an address of the memory cell in which the second data is stored if the second data does not match the first data to correct said write error. - View Dependent Claims (11)
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12. A method of correcting write errors after a write operation in a memory circuit, the method comprising:
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loading an address of a memory cell in which a second data is stored if the second data does not match a first data after a write operation; sensing the second data; inverting said second data; and writing said inverted second data to an address of the memory cell in which the second data is stored to correct said write error.
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Specification