Low-power policy for port

• US 8,456,992 B2
• Filed: 11/03/2009
• Issued: 06/04/2013
• Est. Priority Date: 10/07/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ding, Jin, Kwan, Bruce
• Primary Examiner(s): Hamza, Faruk
• Assistant Examiner(s): DECKER, CASSANDRA L
• Application Number:
  US12/611,717
• Publication Number:
  US 20110080919A1
• Time in Patent Office: 1,309 Days
• Field of Search: None
• US Class Current: 370/232
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Various example embodiments are disclosed. According to an example embodiment, a method may include determining, by a port processor, a buffer length based on an amount of data stored in a port controlled by the port processor, comparing the buffer length to a low-power buffer threshold, determining a link utilization based on a number of packets transmitted by the port, comparing the link utilization to a link utilization threshold, and placing the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold.

Claims

1. A port processor comprising:

a register file comprising;

a buffer length register;

a low-power buffer threshold register;

a timer expiration buffer threshold register;

an aging timer register;

an active buffer threshold register;

a link utilization register; and

a link utilization threshold register storing a link utilization threshold;

an arithmetic/logical unit (ALU) configured to;

update a buffer length stored by the buffer length register based on an amount of data stored for a port controlled by the port processor;

compare the buffer length to the low-power buffer threshold;

update a link utilization stored by the link utilization register based on a number of packets transmitted by the port over a link utilization time interval;

compare the link utilization to the link utilization threshold;

place the port into a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold; and

when the port is in the low-power state;

remove the port from the low-power state based on either of the following conditions;

comparing the buffer length to a timer expiration buffer threshold stored in the timer expiration buffer threshold register upon expiration of an aging timer stored by the aging timer register; and

comparing the buffer length to an active buffer threshold stored in the active buffer threshold register.

2. The port processor of claim 1, wherein placing the port into the low-power state includes placing the port into the low-power state based on the buffer length being less than the low-power buffer threshold and the link utilization being less than the link utilization threshold.

3. The port processor of claim 1, wherein the placing the port into the low-power state includes instructing the port to cease transmission of packets.

4. The port processor of claim 1, wherein the port processor is included in the port, the port being configured to receive the packets from a memory management unit.

5. The port processor of claim 1, wherein the timer expiration buffer threshold is less than the active buffer threshold.

6. An apparatus comprising:

a first port processor, the first port processor being configured to;

determine a first buffer length based on an amount of data stored for a first port controlled by the first port processor;

compare the first buffer length to a first low-power buffer threshold;

determine a first link utilization based on a number of packets transmitted by the first port;

compare the first link utilization to a first link utilization threshold;

place the first port in a first low-power state based on the comparison of the first buffer length to the first low-power buffer threshold and the comparison of the first link utilization to the first link utilization threshold;

when the first port is in the first low-power state;

remove the first port from the first low-power state based on either of the following conditions;

comparing the first buffer length to a first timer expiration buffer threshold upon expiration of a first aging timer; and

comparing the first buffer length to a first active buffer threshold; and

a second port processor, the second port processor being configured to;

determine a second buffer length based on an amount of data stored for a second port controlled by the second port processor;

compare the second buffer length to a second low-power buffer threshold;

determine a second link utilization based on a number of packets transmitted by the second port;

compare the second link utilization to a second link utilization threshold;

place the second port in a second low-power state based on the comparison of the second buffer length to the second low-power buffer threshold and the comparison of the second link utilization to the second link utilization threshold;

when the second port is in the second low-power state;

remove the second port from the second low-power state based on either of the following conditions;

comparing the second buffer length to a second timer expiration buffer threshold upon expiration of a second aging timer; and

comparing the second buffer length to a second active buffer threshold;

wherein the first low-power threshold is different than the second low-power threshold.

7. The apparatus of claim 6, wherein:

the first active buffer threshold is different than the second active buffer threshold.

8. The apparatus of claim 7, wherein the first link utilization threshold is different than the second link utilization threshold.

9. The apparatus of claim 6 wherein the first link utilization threshold is different than the second link utilization threshold.

10. The apparatus of claim 6, further comprising:

the first port configured to transmit packets and cease transmission of packets upon entering the first low-power state; and

the second port configured to transmit packets and cease transmission of packets upon entering the second low-power state.

11. The apparatus of claim 6, wherein the apparatus operates according to an IEEE 802.3az Energy Efficient Ethernet (EEE) protocol.

12. The apparatus of claim 6, wherein the first port processor further includes:

a first buffer length register configured to store the first buffer length;

a first low-power buffer threshold register configured to store the first low-power buffer threshold;

a first link utilization register configured to store the first link utilization; and

a first link utilization threshold register configured to store the first link utilization threshold;

wherein the first port processor is configured to;

update the first buffer length register in response to receiving a first buffer length signal from the first port;

update the first link utilization register based on the number of packets transmitted by the first port;

compare the first buffer length stored in the first buffer length register to the first low-power buffer threshold stored in the first low-power buffer threshold register;

compare the first link utilization stored in the first link utilization register to the first link utilization threshold stored in the first link threshold register; and

place the first port in the first low-power state based on;

the comparison of the first buffer length to the first low-power buffer threshold; and

the comparison of the first link utilization to the first link utilization threshold.

13. The apparatus of claim 12, wherein the first port processor further includes:

an aging interval register configured to store a value corresponding to a number of clock cycles in an aging interval; and

a first aging timer register configured for storing the first aging timer,

wherein the first port processor is configured to;

decrement the first aging timer register at each clock cycle;

remove the first port from the first low-power state when the first aging timer register reaches an aging timer floor if the first buffer length exceeds the first timer expiration buffer threshold; and

restore the first aging timer register to the value stored in the aging interval register when the first aging timer register reaches the aging timer floor.

14. The apparatus of claim 6, wherein:

the first aging timer is configured to determine when a first aging interval has expired,

wherein the first port processor is configured to respond to the first aging interval'"'"'s expiration by;

determining whether the first buffer length is non-zero; and

removing the first port from the first low-power state if the first buffer length is non-zero.

15. The apparatus of claim 6, further comprising:

a memory management unit, the memory management unit including;

a shared memory configured to store packets destined for the first port or the second port; and

a dedicated memory configured to store packets destined for the first port,

the memory management unit being configured to determine whether to forward the packets to the first port or the second port.

16. The apparatus of claim 6, wherein the first timer expiration buffer threshold is less than the first active buffer threshold.

17. An apparatus comprising:

a port processor, the port processor being configured to;

determine a buffer length based on an amount of data stored for a port controlled by the port processor;

compare the buffer length to a low-power buffer threshold;

determine a link utilization based on a number of packets transmitted by the port;

compare the link utilization to a link utilization threshold; and

place the port in a low-power state based on the comparison of the buffer length to the low-power buffer threshold and the comparison of the link utilization to the link utilization threshold; and

when the port is in the low-power state;

remove the port from the low-power state based on either of the following conditions;

comparing the buffer length to a timer expiration buffer threshold upon expiration of an aging timer; and

comparing the buffer length to an active buffer threshold.

18. The port processor of claim 17, wherein the timer expiration buffer threshold is less than the active buffer threshold.