Hierarchical network topology

• US 8,457,135 B2
• Filed: 05/03/2011
• Issued: 06/04/2013
• Est. Priority Date: 03/26/2009
• Status: Expired due to Fees

• Current Assignee: Terascale Supercomputing Inc.
• Original Assignee: Terascale Supercomputing Inc.
• Inventors: Henry, Ronald Michael, Merryfield, Vernonica Frances
• Primary Examiner(s): Chung, Hoon J
• Application Number:
  US13/099,898
• Publication Number:
  US 20110206053A1
• Time in Patent Office: 763 Days
• Field of Search: 370/252, 370/255, 370/256, 370/360, 370/362, 370/380, 370386-388, 370/400, 370/407, 370/422, 370/425, 709/243, 709/244, 709/252
• US Class Current: 370/400
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 2101/604 Address structures or formats
• CPC Class Codes: H04L 45/04 Interdomain routing, e.g. hierarchical routing
• CPC Class Codes: H04L 45/06 Deflection routing, e.g. hot-potato routing
• CPC Class Codes: H04L 61/50 Address allocation

Abstract

A network including a hierarchical structure of nodes is described. The structure of nodes includes n layers including n−1 layers of switch nodes and 1 layer of computational nodes. Each layer in the structure can include m^n-L nodes grouped into units, where m represents a number of nodes in a unit and L represents a layer in the structure, where L=0 represents a lowest layer and L=n−1 represents a highest layer. Each node in a layer other than the computational layer can include a switch node for a unit in a next lower layer. For each unit, each node can be connected to each other node by a point to point link and to a local switch node for the unit by a point to point link. Each node can be connected to each other node and to the local switch node by a local broadcast network for the unit.

Claims

1. A network comprising:

a hierarchical structure of nodes comprising n layers including n−

1 layers of switch nodes and 1 layer of computational nodes, where n is an integer greater than 1, where each layer in the structure includes one or more units of nodes and where L represents a layer in the structure and is an integer with L=0 representing a lowest layer and L=n−

1 representing a highest layer and a number of nodes in a unit is greater than 1;

wherein each node in a layer other than the computational layer comprises a switch node for a unit in a next lower layer in the structure and wherein each switch node is configured to receive a packet from a first node and transfer the packet to a second node without copying at the switch node data included in the packet; and

wherein for each unit;

each node in the unit is connected to each other node in the unit by a point to point link;

each node in the unit is connected to a local switch node for the unit by a point to point link; and

each node in the unit is connected to each other node in the unit and to the local switch node by a local broadcast network for the unit.

2. The network of claim 1, wherein one or more point to point links included in one or more units are deactivated.

3. The network of claim 1, wherein each unit of a layer in the structure has the same number of nodes.

4. The network of claim 1, wherein each unit of each layer in the structure has the same number of nodes.

5. The network of claim 4, wherein each unit comprises a local, three-dimensional network topology represented by a 2×

2×

2 cube including 8 nodes.

6. The network of claim 4, wherein each computational node comprises a processing element operable to perform instructions of one or more applications.

7. The network of claim 1, wherein the lowest layer in the structure is the layer of computational nodes.

8. The network of claim 1, wherein each node in the unit is connected to each other node in the unit and to the local switch node by an Ethernet network.

9. The network of claim 1, wherein each computational node comprises a processing element, a controller, and memory.

10. The network of claim 1, wherein each computational node comprises communication hardware implemented as a field programmable gate array.