Iterative interference suppression using mixed feedback weights and stabilizing step sizes

• US 8,457,262 B2
• Filed: 06/28/2011
• Issued: 06/04/2013
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: III Holdings 1, LLC
• Original Assignee: Rambus Inc.
• Inventors: Guess, Tommy, McCloud, Michael L., Nagarajan, Vijay, Lamba, Gagandeep Singh
• Primary Examiner(s): Kim, Kevin
• Application Number:
  US13/170,824
• Publication Number:
  US 20110255573A1
• Time in Patent Office: 707 Days
• Field of Search: 375/346, 375/347, 375/348, 375/349
• US Class Current: 375/346
• CPC Class Codes: H04B 1/7107 Subtractive interference cancellation
• CPC Class Codes: H04B 1/71072 Successive interference cancellation
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 1/715 Interference-related aspects
• CPC Class Codes: H04L 2025/03375 Passband transmission
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference

Abstract

A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimate. Receiver embodiments may be implemented explicitly in software of programmed hardware, or implicitly in standard Rake-based hardware either within the Rake (i.e., at the finger level) or outside the Rake (i.e., at the user of subchannel symbol level).

Claims

1. An interference suppressor configured for computing interference-suppressed symbol estimates and performing processing during each of at least one iteration, the suppressor comprising

a processor configured for

calculating a stabilizing step size having a magnitude that is a function of at least a received signal;

and

weighting an error signal with the stabilizing step size;

wherein the stabilizing step size is characterized by

2. The interference suppressor recited in claim 1, wherein the processor further is configured to calculate the stabilizing step size as a function of the received signal and a synthesized received signal.

3. The interference suppressor recited in claim 2, wherein the processor further is configured to calculate the error signal as a difference between the received signal and the synthesized received signal.

4. The interference suppressor recited in claim 1, wherein the processor further is configured to calculate the stabilizing step size as a ratio of distance measurements between a received signal and at least one synthesized received signal.

6. The interference suppressor recited in claim 4, wherein the stabilizing step size is characterized by

7. The interference suppressor recited in claim 1, wherein the processor further is configured for employing a plurality of methods for calculating the stabilizing step.

8. The interference suppressor recited in claim 1, wherein the processor further is configured for calculating the stabilizing step as a function of channel-quality parameters.

9. The interference suppressor recited in claim 8, wherein the stabilizing step size is characterized by

10. The interference suppressor recited in claim 1, wherein the processor further is configured to set the stabilizing step size equal to a predetermined fixed value.

5. An interference suppressor configured for computing interference-suppressed symbol estimates and performing processing during each of at least one iteration, the suppressor comprising

a processor configured for

calculating a stabilizing step size having a magnitude that is a function of at least a received signal;

weighting an error signal with the stabilizing step size;

calculating the stabilizing step size as a ratio of distance measurements between a received signal and at least one synthesized received signal;

calculating a first error vector for evaluating a first error signal as a difference between the received signal and a first synthesized received signal;

receiving from a Rake receiver a first plurality of resolved signals, wherein the first plurality of resolved signals correspond to each symbol source in a channel;

combining the first plurality of resolved signals to produce a first combined signal;

despreading the first combined signal into a first column vector;

calculating a second error vector as a difference between the received signal and a second synthesized received signal,

receiving from a Rake receiver a second plurality of resolved signals, wherein the second plurality of resolved signals correspond to each symbol source in the channel;

combining the second plurality of resolved signals to produce a second combined signal,

despreading the second combined signal into a second column vector;

scaling the first error vector with soft weights for producing a weighted first error vector;

evaluating an inner product between this weighted first error vector and the second error vector,

employing the inner product in the numerator; and

producing a synthesized received signal calculated from modeling a transmitted version of the first error vector,

producing a resolved composite signal,

producing a square magnitude of the resolved composite signal, and

integrating the square magnitude to calculate the denominator.

11. An interference suppression method comprising:

configuring a processor for

computing interference-suppressed symbol estimates; and

applying stabilizing step sizes to an error signal during each of at least one iteration;

wherein applying stabilizing step sizes comprises calculating a stabilizing step size having a magnitude that is a function of at least a received signal; and

wherein the stabilizing step size is characterized by

12. The method recited in claim 11, wherein configuring the processor for calculating a stabilizing step size comprises configuring the processor for calculating the stabilizing step size as a function of the received signal and a synthesized received signal.

13. The method recited in claim 12, wherein the error signal is calculated as a difference between the received signal and the synthesized received signal.

14. The method recited in claim 11, wherein calculating a stabilizing step size comprises calculating the stabilizing step size as a ratio of distance measurements between a received signal and at least one synthesized received signal.

15. The method recited in claim 14, wherein the ratio comprises a numerator and a denominator, and wherein calculating a stabilizing step size comprises:

calculating a first error vector for evaluating a first error signal as a difference between the received signal and a first synthesized received signal;

receiving from a Rake receiver a first plurality of resolved signals, wherein the first plurality of resolved signals correspond to each symbol source in a channel;

combining the first plurality of resolved signals to produce a first combined signal;

despreading the first combined signal into a first column vector;

calculating a second error vector as a difference between the received signal and a second synthesized received signal,

receiving from a Rake receiver a second plurality of resolved signals, wherein the second plurality of resolved signals correspond to each symbol source in the channel;

combining the second plurality of resolved signals to produce a second combined signal,

despreading the second combined signal into a second column vector;

scaling the first error vector with soft weights for producing a weighted first error vector;

evaluating an inner product between this weighted first error vector and the second error vector,

employing the inner product in the numerator; and

producing a synthesized received signal calculated from modeling a transmitted version of the first error vector,

producing a resolved composite signal,

producing a square magnitude of the resolved composite signal, and

integrating the square magnitude to calculate the denominator.

16. The method recited in claim 14, wherein calculating a stabilizing step size is configured to produce a stabilizing step size characterized by

17. The method recited in claim 11, wherein calculating a stabilizing step size comprises a plurality of methods for calculating the stabilizing step.

18. The method recited in claim 11, wherein calculating a stabilizing step size is configured for employing a function of channel-quality parameters to calculate the stabilizing step.

19. The method recited in claim 18, wherein the stabilizing step size is characterized by

20. The method recited in claim 11, wherein calculating the stabilizing step size comprises setting the stabilizing step equal to a predetermined fixed value.

21. A computer-readable medium storing a computer program implementing the method of claim 11.