Memory address generating method and twiddle factor generator using the same
First Claim
1. A twiddle factor generator for generating a final twiddle factor value for an nth twiddle factor in a fast Fourier transform (FFT) system, the twiddle factor generator comprising:
- a hardware memory address calculator for generating a temporary address value for the nth twiddle factor, generating a twiddle factor memory address value for the nth twiddle factor based on the temporary address value, and outputting a control signal based on the temporary address value;
a twiddle factor storage unit for storing a twiddle factor value corresponding to the twiddle factor memory address value for the nth twiddle factor, the twiddle factor value generated based on a previously generated twiddle factor value, and outputting the twiddle factor value as a real part and an imaginary part; and
a controller for outputting the final twiddle factor value to the FFT system based on the control signal output from the memory address calculator and the twiddle factor value output from the twiddle factor storage unit,wherein the memory address calculator generates the temporary address value for the nth twiddle factor by;
calculating a multiplied value by multiplying a sign value of the nth twiddle factor and a parameter value indicating a twiddle factor case; and
adding the multiplied value to a twiddle factor memory address value for an (n-1)th twiddle factor.
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Accused Products
Abstract
The present invention relates to a memory address generating method and a twiddle factor generator using the memory address generating method in a fast Fourier transform (FFT) system. In the memory address generating method for generating a memory address of a twiddle factor in a fast Fourier transform (FFT) system according to an embodiment of the present invention: a) a temporary address value of a second twiddle factor is induced and generated based on a first twiddle factor; b) a control signal for controlling the system is generated based on the generated temporary address value; and c) a memory address value of the second twiddle factor is generated from the temporary address value.
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Citations
18 Claims
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1. A twiddle factor generator for generating a final twiddle factor value for an nth twiddle factor in a fast Fourier transform (FFT) system, the twiddle factor generator comprising:
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a hardware memory address calculator for generating a temporary address value for the nth twiddle factor, generating a twiddle factor memory address value for the nth twiddle factor based on the temporary address value, and outputting a control signal based on the temporary address value; a twiddle factor storage unit for storing a twiddle factor value corresponding to the twiddle factor memory address value for the nth twiddle factor, the twiddle factor value generated based on a previously generated twiddle factor value, and outputting the twiddle factor value as a real part and an imaginary part; and a controller for outputting the final twiddle factor value to the FFT system based on the control signal output from the memory address calculator and the twiddle factor value output from the twiddle factor storage unit, wherein the memory address calculator generates the temporary address value for the nth twiddle factor by; calculating a multiplied value by multiplying a sign value of the nth twiddle factor and a parameter value indicating a twiddle factor case; and adding the multiplied value to a twiddle factor memory address value for an (n-1)th twiddle factor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for generating a twiddle factor memory address value for an nth twiddle factor and a control signal in a fast Fourier transform (FFT) system, the method comprising:
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generating a temporary address value of the nth twiddle factor; generating the control signal for controlling the FFT system based on the temporary address value of the nth twiddle factor; and outputting, by a hardware memory address calculator, the twiddle factor memory address value for the nth twiddle factor to a twiddle factor storage unit after generating the twiddle factor memory address value based on the temporary address value, and outputting the control signal to a controller, wherein the generating the temporary address value of the nth twiddle factor comprises; calculating a multiplied value by multiplying a sign value of the nth twiddle factor and a parameter value indicating a twiddle factor case; and adding the multiplied value to a twiddle factor memory address value for an (n-1)th twiddle factor, wherein the twiddle factor storage unit outputs a twiddle factor value corresponding to the twiddle factor memory address value for the nth twiddle factor, the twiddle factor value generated based on a previously generated twiddle factor value, and wherein the controller outputs a final twiddle factor value to the FFT system based on the control signal output from the memory address calculator and the twiddle factor value output from the twiddle factor storage unit. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method for generating a final twiddle factor value for an nth twiddle factor in a fast Fourier transform (FFT) system, the method comprising:
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generating a temporary address value of the nth twiddle factor; generating a control signal for controlling the FFT system based on the temporary address value of the nth twiddle factor; outputting, by a hardware memory address calculator, a twiddle factor memory address value for the nth twiddle factor after generating the twiddle factor memory address value based on the temporary address value, and outputting the control signal; outputting, from a twiddle factor storage unit, a twiddle factor value corresponding to the twiddle factor memory address value for the nth twiddle factor, the twiddle factor value generated based on a previously generated twiddle factor value; and outputting the final twiddle factor value to the FFT system based on the control signal output from the memory address calculator and the twiddle factor value output from the twiddle factor storage unit, wherein the generating the temporary address value of the nth twiddle factor comprises; calculating a multiplied value by multiplying a sign value of the nth twiddle factor and a parameter value indicating a twiddle factor case; and adding the multiplied value to a twiddle factor memory address value for an (n-1)th twiddle factor.
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Specification