Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
First Claim
1. Digital signal processing (“
- DSP”
) block circuitry comprising;
first multiplier circuitry for producing a first plurality of parallel output signals indicative of a first multiplication product;
first systolic delay circuitry for delaying the first plurality of parallel output signals by a systolic delay time interval;
second multiplier circuitry for producing a second plurality of parallel output signals indicative of a second multiplication product; and
adder circuitry for adding (1) outputs of the first systolic delay circuitry, (2) the second plurality of parallel output signals, and (3) a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry.
1 Assignment
0 Petitions
Accused Products
Abstract
Digital signal processing (“DSP”) block circuitry on an integrated circuit (“IC”) is adapted for use (e.g., in multiple instances of the DSP block circuitry on the IC) for implementing finite-impulse-response (“FIR”) digital filters in systolic form. Each DSP block may include (1) first and second multiplier circuitry and (2) adder circuitry for adding (a) outputs of the multipliers and (b) signals chained in from a first other instance of the DSP block circuitry. Systolic delay circuitry is provided for either the outputs of the first multiplier (upstream from the adder) or at least one of the sets of inputs to the first multiplier. Additional systolic delay circuitry is provided for outputs of the adder, which are chained out to a second other instance of the DSP block circuitry.
241 Citations
12 Claims
-
1. Digital signal processing (“
- DSP”
) block circuitry comprising;first multiplier circuitry for producing a first plurality of parallel output signals indicative of a first multiplication product; first systolic delay circuitry for delaying the first plurality of parallel output signals by a systolic delay time interval; second multiplier circuitry for producing a second plurality of parallel output signals indicative of a second multiplication product; and adder circuitry for adding (1) outputs of the first systolic delay circuitry, (2) the second plurality of parallel output signals, and (3) a third plurality of parallel signals indicative of a data value received from a first other instance of said DSP block circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- DSP”
Specification