Methods and systems for handling inter-process and inter-module communications in servers and server clusters

• US 8,458,390 B2
• Filed: 03/26/2012
• Issued: 06/04/2013
• Est. Priority Date: 02/13/2004
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Mehrotra, Sharad, Lovett, Thomas Dean, Nicolaou, Cosmos, Saraiya, Nakul Pratap, Shah, Shreyas B.
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US13/430,158
• Publication Number:
  US 20130103880A1
• Time in Patent Office: 435 Days
• Field of Search: 710 8- 19, 710104-105, 710306-317, 710 39- 41, 709/238, 709/248, 709/250, 709/230, 709/236
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/45 Arrangements for providing or supporting expansion
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04L 49/70 Virtual switches

Abstract

Pluggable modules communicate via a switch fabric dataplane accessible via a backplane. Various embodiments are comprised of varying numbers and arrangements of the pluggable modules in accordance with a system architecture that provides for provisioning virtual servers and clusters of servers from underlying hardware and software resources. The system architecture is a unifying solution for applications requiring a combination of computation and networking performance. Resources may be pooled, scaled, and reclaimed dynamically for new purposes as requirements change, using dynamic reconfiguration of virtual computing and communication hardware and software.

Claims

1. A system for communicating a packet, the system comprising:

means for converting a packet into cells within an input/output interface, each cell specifying a destination physical address corresponding to a first physical partition of a physically-partitionable symmetric multiprocessor;

means for transferring each cell through a switch in accordance with the destination address;

means for forming the cells into a reconstructed packet within the first physical partition;

wherein the physically-partitionable symmetric multiprocessor is programmable as a selected one of a first configuration comprising one physical partition and a second configuration comprising a plurality of physical partitions;

wherein the packet has a destination logical address and the destination physical address of each cell corresponding to the packet is based at least in part on the destination logical address of the packet;

wherein the forming of the cells into a reconstructed packet comprises data transfers according to a direct memory access protocol; and

wherein the input/output interface comprises at least one of a network interface and a storage interface.

2. The system of claim 1, wherein the physically-partitionable symmetric multiprocessor is programmed in the first configuration and the first physical partition is the only physical partition.

3. The system of claim 1, wherein the physically-partitionable symmetric multiprocessor is programmed in the second configuration and the first physical partition is one of the plurality of physical partitions.

4. A system of directing a packet to a process executing on a symmetric multi-processor, the system comprising:

in an input/output interface, means for receiving a packet comprising a destination address;

means for dividing the packet into a plurality of cells wherein each cell has a fabric address specifying an egress port of a switch fabric and wherein each fabric address is based at least in part on the packet destination address;

means for routing each cell via the switch fabric in accordance with each cell fabric address;

means for forming the routed cells into a reconstructed packet directly provided to the process executing on the symmetric multi-processor;

wherein the symmetric multi-processor is programmable as a selected one of a first configuration comprising one physical partition and a second configuration comprising a plurality of physical partitions, each of the configurations thereby comprising at least a first physical partition, and the process executes in the first physical partition;

wherein the directly providing the reconstructed packet comprises data transfers according to a direct memory access protocol; and

wherein the input/output interface comprises at least one of a network interface and a storage interface.

5. A system, comprising:

in a first compute module, a first fabric interface connected to a switch fabric and a first symmetric multi-processor connected to the first fabric interface, the first fabric interface comprising means for directly receiving a first-to-second packet from a first send process executing on the first symmetric multi-processor, the first fabric interface further comprising means for cellifying the first-to-second packet into first-to-second cells and emitting the first-to-second cells to the switch fabric, each cell comprising a respective fabric address specifying an egress port of the switch fabric, each fabric address being based at least in part on a first-to-second packet destination address included within the first-to-second packet;

in a second compute module, a second fabric interface connected to the switch fabric and a second symmetric multi-processor connected to the second fabric interface, the second fabric interface comprising means for directly receiving a second-to-first packet from a second send process executing on the second symmetric multi-processor, the second fabric interface further comprising means for cellifying the second-to-first packet into second-to-first cells and emitting the second-to-first cells to the switch fabric, each cell comprising a respective fabric address specifying an egress port of the switch fabric, each fabric address being based at least in part on a second-to-first packet destination address included within the second-to-first packet;

in the switch fabric, means for receiving the first-to-second cells and the second-to-first cells and routing each cell in accordance with its respective fabric address;

in the first compute module, the first fabric interface further comprising means for receiving the second-to-first cells, forming the received second-to-first cells into a reconstructed second-to-first packet, and directly providing the reconstructed second-to-first packet to a first receive process executing on the first symmetric multi-processor;

in the second compute module, the second fabric interface further comprising means for receiving the first-to-second cells, forming the received first-to-second cells into a reconstructed first-to-second packet, and directly providing the reconstructed first-to-second packet to a second receive process executing on the second symmetric multi-processor;

wherein each of the first symmetric multi-processor and the second symmetric multi-processor are programmable as a selected one of at least a first configuration comprising one physical partition and a second configuration comprising a plurality of physical partitions;

wherein the directly receiving the first-to-second packet and the second-to-first packet comprises data transfers according to a direct memory access read protocol; and

wherein the directly providing the reconstructed first-to-second packet and the reconstructed second-to-first packet comprises data transfers according to a direct memory access write protocol.