Device and memory system for memory management using access frequency information

• US 8,458,436 B2
• Filed: 01/30/2012
• Issued: 06/04/2013
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kunimatsu, Atsushi, Nakai, Hiroto, Sakamoto, Hiroyuki, Maeda, Kenichi
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/360,903
• Publication Number:
  US 20120124290A1
• Time in Patent Office: 491 Days
• Field of Search: 711/103
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Claims

1. A memory management device connectable to a non-volatile memory and a processor comprising:

an address conversion unit converting logical addresses from the processor into physical addresses of the non-volatile memory; and

an access unit reading data from memory areas of the non-volatile memory designated by physical addresses at reading, and writing data to memory areas of the non-volatile memory designated by physical addresses at writing,

wherein the non-volatile memory includes at least two regions and the access unit determines which region to write writing data based on access frequency information associated with the writing data, and the access frequency information is determined based on a predetermined value set according to a characteristic of the writing data.

2. The device according to claim 1, wherein the access frequency information associated with the writing data is determined based on whether the writing data is a part of cache information of web browser information.

3. The device according to claim 1, wherein the access frequency information associated with the writing data is determined based on a predetermined access pattern associated with the writing data.

4. A memory system connectable to a processor comprising:

a non-volatile memory;

a memory management device configured to manage the non-volatile memory, comprising,

an address conversion unit converting logical addresses from the processor into physical addresses of the non-volatile memory; and

an access unit reading data from memory areas of the non-volatile memory designated by physical addresses at reading, and writing data to memory areas of the non-volatile memory designated by physical addresses at writing,

wherein the non-volatile memory includes at least two regions, and the access unit determines which region to write writing data based on access frequency information associated with the writing data, and the access frequency information is determined based on a predetermined value set according to a characteristic of the writing data.

5. The memory system according to claim 4, wherein the access frequency information associated with the writing data is determined based on whether the writing data is a part of cache information of web browser information.

6. The memory system according to claim 4, wherein the access frequency information associated with the writing data is determined based on a predetermined access pattern associated with the writing data.