Methods for manufacturing trench MOSFET with implanted drift region

• US 8,461,001 B2
• Filed: 12/09/2009
• Issued: 06/11/2013
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US12/653,131
• Publication Number:
  US 20100087039A1
• Time in Patent Office: 1,280 Days
• Field of Search: 438/268, 438/270, 438/272, 438/138, 438/589, 257/E21.41
• US Class Current: 438/268
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.

Claims

1. A method for manufacturing a trenched semiconductor power device comprising plurality of trenched gates surrounded by source regions near a top surface of an epitaxial layer encompassed in body regions, wherein said epitaxial layer is supported on a semiconductor substrate, said method comprising:

carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding said trenches to provide drift regions below body regions and above said epitaxial layer for on-resistance reduction, and preventing a degraded breakdown voltage with a thicker oxide along a lower portion of trench sidewall and bottom wherein the thicker oxide having a greater thickness than an oxide layer along an upper portion of said trench sidewalls, and wherein the trenches have trench bottoms disposed below said drift regions extended downwardly to said epitaxial layer.

2. The method of claim 1 wherein:

said step of carrying out said tilt-angle implantation through said sidewalls of said trenches further comprising a step of carrying out a tilt-angle implantation with a tilt-angle ranging between 4 to 30 degrees to prevent dopant of said tilt-angle implantation from entering into trench bottoms of said trenches.

3. The method of claim 1 wherein:

said step of carrying out said tilt-angle implantation through said sidewalls of said trenches further comprising a step of carrying out a tilt angle implantation of a N dopant for manufacturing an N-channel MOSFET device having N-type tilt-angle implanted drift regions in an N-epitaxial layer supported on a N+ substrate.

4. The method of claim 1 wherein:

said step of carrying out said tilt-angle implantation through said sidewalls of said trenched further comprising a step of carrying out a tilt angle implantation of a P dopant for manufacturing a P-channel MOSFET device having P-type tilt-angle implanted drift regions in a P-epitaxial layer supported on a P+ substrate.

5. The method of claim 1 further comprising:

forming guard rings at a termination area for manufacturing said semiconductor power device have a breakdown voltage greater than fifty volts having a breakdown voltage ranging between fifty to two hundreds volts.

6. The method of claim 1 further comprising:

forming a field plate at a termination area for operating at a breakdown voltage ranging between eight volts to fifty volts.

7. The method of claim 1 further comprising:

forming a thicker oxide layer on sidewalls of a lower portion of said trenches and a thinner oxide layer on sidewalls at an upper portion of said trenches.

8. The method of claim 1 further comprising:

forming a bottom portion of said trenched gates having a smaller width and padded with a thicker gate oxide layer on sidewalls of said bottom portion of trenched gates and forming a top, portion of said trenched gates having a greater width and padded with a thinner gate oxide layer on sidewalls of said top portion of said trenched gates.

9. The method of claim 1 further comprising:

forming said epitaxial layer having a resistivity ranging between 0.3 to 3.0 ohm-cm and manufacturing said trenched semiconductor power device having a breakdown voltage ranging between 8 to 200 volts.

10. The method of claim 1 further includes a step of:

forming each of said trenched gates as a split gate comprising a bottom gate segment and a top gate segment insulated by an inter-segment insulation layer.

11. The method of claim 10 further comprising:

padding each said bottom gate segment by a thicker oxide layer on sidewalls of a lower portion of said trenched gates and padding each said top gate segment by a thinner oxide layer on sidewalls at an upper portion of said trenched gates.