Method for fabrication of a semiconductor device and structure

• US 8,461,035 B1
• Filed: 09/30/2010
• Issued: 06/11/2013
• Est. Priority Date: 09/30/2010
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Cronquist, Brian, Beinglass, Isreal, de Jong, Jan Lodewijk, Sekar, Deepak C., Or-Bach, Zvi
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): CHOI, CALVIN Y
• Application Number:
  US12/894,235
• Time in Patent Office: 985 Days
• Field of Search: 438/455, 438/458, 438/459
• US Class Current: 438/599
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/082 including bipolar components only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method for fabricating a device, the method including: providing a first layer including first transistors wherein the first transistors include mono-crystalline semiconductor and first alignment marks; overlaying a second semiconductor layer over the first layer, wherein the second layer includes second transistors, the second transistors include mono-crystalline semiconductor and are configured to be memory cells, at least one of the memory cells include a floating body region configured to be charged to a level indicative of a state of the memory cell, and fabricating the second transistors includes alignment to the first alignment marks.

Claims

1. A method for fabricating a device, the method comprising:

providing a first layer comprising first transistors wherein said first transistors comprise mono-crystalline semiconductor;

fabricating a first metal layer overlaying said first layer and aligned to said first transistors;

fabricating a second metal layer overlaying said first metal layer and aligned to said first metal layer;

fabricating a third metal layer overlaying said second metal layer and aligned to said second metal layer; and

fabricating a second layer overlaying said third metal layer wherein said second layer comprises second transistors wherein said second transistors comprise mono-crystalline semiconductor, and

wherein said second metal layer has a substantially higher current carrying capability than said first metal layer and said third metal layer.

2. The method according to claim 1, wherein said second layer has been transferred using an ion-cut layer transfer process.

3. The method according to claim 1, wherein said second transistors are horizontally oriented transistors.

4. The method according to claim 1, wherein said second transistors have side gates.

5. The method according to claim 1, further comprising,

processing an isolation layer overlaying said second layer, and

processing a third layer overlaying said isolation layer,

wherein said third layer comprises third transistors, and

wherein said third transistors are aligned to overlay said second transistors.