Method of forming shielded gate power transistor utilizing chemical mechanical planarization

• US 8,461,040 B2
• Filed: 03/07/2011
• Issued: 06/11/2013
• Est. Priority Date: 01/05/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E., Ridley, Rodney S., Kraft, Nathan Lawrence
• Primary Examiner(s): Pham, Thanh V
• Application Number:
  US13/042,292
• Publication Number:
  US 20120058615A1
• Time in Patent Office: 827 Days
• Field of Search: 438/39, 438/42, 438/626, 438/631, 438/645, 257/E21.304
• US Class Current: 438/626
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer

Abstract

A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.

Claims

1. A method of forming a shielded gate field effect transistor comprising:

forming a plurality of active gate trenches in a silicon region;

lining lower sidewalls and bottom of the active gate trenches with a shield dielectric;

using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon;

forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches;

lining upper sidewalls of the active gate trenches with a gate dielectric; and

forming a gate electrode over the IPD in an upper portion of the active gate trenches.

2. The method of claim 1 wherein the step of filling a bottom portion of the active gate trenches comprises:

forming a polysilicon layer filling the active gate trenches and extending over mesa regions adjacent the active gate trenches;

using a CMP process, etching back the polysilicon with the shield dielectric serving as a CMP stop layer; and

recessing the polysilicon into the active gate trenches to a predetermined depth to thereby form the shield electrodes along a bottom portion of the active gate trenches.

3. The method of claim 1 further comprising:

forming a shield runner trench simultaneously with forming the plurality of active gate trenches, the shield runner trench extending perpendicular to but contiguous with the active gate trenches.

4. The method of claim 3 wherein the step of filling a bottom portion of the active gate trenches comprises:

forming a polysilicon layer filling the active gate trenches and the shield runner trench and extending over mesa regions adjacent the active gate trenches and shield runner trench;

using a CMP process, etching back the polysilicon with the shield dielectric serving as a CMP stop layer; and

using a masking layer to cover the shield runner trench, recessing the polysilicon into the active gate trenches to a predetermined depth to thereby form the shield electrodes along a bottom portion of the active gate trenches.

5. The method of claim 4 wherein during the etching back step, when the shield dielectric is exposed, the CMP process is continued for a predetermined period of time to recess the polysilicon in the active gate trenches and the shield runner trench to just below a top surface of the silicon region.

6. The method of claim 4 further comprising:

after the etching back step but before the polysilicon recessing step, etching the polysilicon in the active gate trenches and the shield runner trench to just below a top surface of the silicon region.

7. The method of claim 3 wherein the shield runner trench is wider than the active gate trenches.

8. The method of claim 3 wherein the shield runner trench has the same width as the active gate trenches.

9. The method of claim 3 wherein the silicon region has a first conductivity type, the method further comprising:

forming a well region of a second conductivity type in the silicon region;

forming source regions of the first conductivity type in the well region; and

forming a metal layer electrically contacting the well region, the source regions, and a shield runner electrode formed in the shield runner trench.

10. The method of claim 1 further comprising:

forming a shield runner trench and a gate runner trench simultaneously with forming the plurality of active gate trenches, the shield runner trench and gate runner trench extending perpendicular to but contiguous with the active gate trenches.

11. The method of claim 10 wherein the shield runner includes a shield runner electrode that is contiguous with and thus electrically connected to the shield electrodes in the active gate trenches, and the gate runner trench includes a gate runner electrode that is contiguous with and thus electrically connected to the gate electrodes in the active gate trenches.

12. The method of claim 1 wherein the IPD is formed using a CMP process.

13. The method of claim 1 wherein the gate electrodes are formed using a CMP process.

14. The method of claim 1 wherein the IPD and gate electrodes are formed using CMP processes.