Bond pad connection to redistribution lines having tapered profiles

• US 8,461,045 B2
• Filed: 03/17/2011
• Issued: 06/11/2013
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Kuo-Ching, Chen, Chen-Shien, Huang, Hon-Lin
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US13/050,424
• Publication Number:
  US 20110165776A1
• Time in Patent Office: 817 Days
• Field of Search: 438/667, 257/621, 257/E23.168, 257/E23.011
• US Class Current: 438/667
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13027 the bump connector being offset with respect to the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL.

Claims

1. A method comprising:

forming a through-silicon via (TSV) penetrating through a semiconductor substrate;

forming a redistribution line (RDL) over a backside of the semiconductor substrate and connected to a back end of the TSV;

forming a passivation layer over the RDL;

patterning the passivation layer to form an opening, wherein a top surface of the RDL and a sidewall of the RDL are exposed through the opening; and

forming a metal finish contacting the top surface and the sidewall of the RDL.

2. The method of claim 1, wherein the step of forming the metal finish comprises plating the metal finish onto the RDL through the opening.

3. The method of claim 1, wherein the RDL has a tapered profile with a top portion of the RDL being narrower than a respective bottom portion of the RDL.

4. The method of claim 3, wherein the step of forming the RDL comprises:

forming a seed layer on the backside of the semiconductor substrate and electrically connected to the back end of the TSV;

forming and patterning a mask layer, wherein first portions of the seed layer are not covered by the mask layer;

forming the RDL by plating a conductive material on the first portions of the seed layer and through the opening;

removing the mask layer; and

after the step of removing the mask layer, etching second portions of the seed layer not covered by the mask layer until the RDL has the tapered profile.

5. The method of claim 4, wherein the step of etching the portions of the seed layer comprises:

etching the seed layer until the second portions of the seed layer not covered by RDL are removed, wherein the step of etching the seed layer takes a first period of time; and

after the step of etching the seed layer, over-etching the RDL until the RDL has the tapered profile, wherein the step of over-etching takes a second period of time equal to about one time to two times the first period of time.

6. The method of claim 1, wherein the back end of the TSV extends into the RDL.

7. The method of claim 1, wherein the RDL comprises:

an RDL strip connected to the TSV; and

an RDL pad having a width greater than a width of the RDL strip, wherein the metal finish contacts a sidewall of the RDL pad.

8. The method of claim 7, wherein substantially all sidewalls of the RDL pad are exposed through the opening, and wherein the metal finish contacts substantially all sidewalls of the RDL pad.

9. The method of claim 1, wherein an edge of the passivation layer facing the sidewall of the RDL is spaced apart from a respective edge of the metal finish.

10. A method comprising:

forming a through-silicon via (TSV) penetrating through a semiconductor substrate, the TSV comprising a back end extending beyond a backside of the semiconductor substrate;

forming a redistribution line (RDL) over the backside of the semiconductor substrate and connected to the back end of the TSV, the RDL comprising;

an RDL strip contacting the TSV; and

an RDL pad having a greater width than the RDL strip, wherein the RDL pad joins the RDL strip;

forming a passivation layer over a portion of the RDL, wherein the passivation layer comprises an opening, with substantially all sidewalls of the RDL pad being exposed through the opening; and

forming a metal finish contacting the substantially all sidewalls of the RDL pad.

11. The method of claim 10, wherein the RDL has a tapered profile with a top portion of the RDL being narrower than a respective bottom portion of the RDL.

12. The method of claim 11, wherein the step of forming the RDL comprises:

forming a seed layer on the backside of the semiconductor substrate and electrically connected to the back end of the TSV;

forming and patterning a mask layer to expose first portions of the seed layer through the mask layer;

forming the RDL by plating a conductive material on the first portions of the seed layer;

removing the mask layer; and

after the step of removing the mask layer, etching second portions of the seed layer not covered by the mask layer until the RDL has the tapered profile.

13. The method of claim 12, wherein the step of etching the second portions of the seed layer comprises etching the seed layer until the second portions of the seed layer are removed, and continue to over-etch the RDL until the RDL has the tapered profile.

14. The method of claim 10, wherein a top surface of the metal finish is higher than a top surface of the passivation layer.

15. A method comprising:

forming a through-silicon via (TSV) penetrating through a semiconductor substrate, the TSV comprising a back end exposed through a backside of the semiconductor substrate;

forming a redistribution line (RDL) over the backside of the semiconductor substrate and connected to the back end of the TSV, wherein the RDL has a tapered profile with a top portion of the RDL being narrower than a respective bottom portion of the RDL;

forming a passivation layer over the RDL;

etching the passivation layer to form an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening; and

forming a metal finish in the opening and contacting the portion of the RDL exposed through the opening.

16. The method of claim 15, wherein the RDL comprises:

an RDL strip connected to the TSV; and

an RDL pad having a width greater than a width of the RDL strip, wherein the RDL pad has a slanted sidewall exposed through the opening in the passivation layer, and wherein the slanted sidewall of the RDL contacts the metal finish.

17. The method of claim 16, wherein after the step of etching the passivation layer, a sidewall of the RDL strip is exposed through the opening, and wherein the metal finish further contacts the sidewall of the RDL strip.

18. The method of claim 16, wherein substantially all sidewalls of the RDL pad contact the metal finish.

19. The method of claim 15, wherein the step of forming the RDL comprises:

forming a seed layer on the backside of the semiconductor substrate and electrically connected to the back end of the TSV;

forming and patterning a mask layer, wherein first portions of the seed layer are not covered by the mask layer;

forming the RDL on the seed layer and through the opening;

removing the mask layer; and

after the step of removing the mask layer, etching second portions of the seed layer until the RDL has the tapered profile.

20. The method of claim 19, wherein the step of etching the portions of the seed layer comprises:

etching the seed layer until the portions of the seed layer not covered by RDL are fully removed, wherein the step of etching the seed layer takes a first period of time; and

after the step of etching the seed layer, over-etching the RDL until the RDL has the tapered profile, wherein the step of over-etching takes a second period of time equal to between about one time and about two times the first period of time.