Semiconductor device manufacturing method

• US 8,461,052 B2
• Filed: 03/28/2011
• Issued: 06/11/2013
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Oohara, Junji, Asami, Kazushi
• Primary Examiner(s): Deo, Duy
• Application Number:
  US13/073,173
• Publication Number:
  US 20110244687A1
• Time in Patent Office: 806 Days
• Field of Search: None
• US Class Current: 438/706
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/32972 Spectral analysis
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32

Abstract

In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Claims

1. A method of manufacturing a semiconductor device comprising:

preparing a wafer having a silicon layer on which a mask having a plurality of openings is located, the plurality of openings having M different widths, where M is a positive integer more than one;

placing the wafer in a chamber; and

forming a plurality of trenches simultaneously in the silicon layer of the wafer through the mask, the plurality of trenches having M different widths defined by the plurality of openings of the mask, wherein

the forming of the plurality of trenches includes alternately and repeatedly performing a passivation step and an etching step,

the passivation step includes depositing a polymer passivation layer on a side wall and a bottom of the plurality of trenches by converting gas introduced in the chamber into plasma,

the etching step includes removing the passivation layer on the bottom of the plurality of trenches until the silicon layer is exposed to the bottom and applying reactive ion etching to the exposed silicon layer to increase a depth of the plurality of trenches,

the etching step further includes setting incident ion energy for the reactive ion etching to a predetermined energy value when the passivation layer on the bottom of the trench having the Nth smallest width is removed, where N is a positive integer less than M, and

the energy value allows the etching amount of the silicon layer at the bottom of the trench having the Nth smallest width to be equal to or greater than the etching amount of the silicon layer at the bottom of the trench having the (N+1)th smallest width within a remaining time of the present etching step.

2. The method according to claim 1, wherein

the energy value allows the passivation layer on the bottom of the trench having the (N+1)th smallest width to be completely removed within the remaining time of the present etching step.

3. The method according to claim 1, wherein

the energy value prevents the passivation layer on the bottom of the trench having the (N+1)th smallest width to be removed.

4. The method according to claim 1, wherein

the forming of the plurality of trenches includes performing a switch from the etching step to the passivation step when the passivation layer on a side wall of the trench having the smallest width is removed.

5. The method according to claim 1, wherein

the forming of the plurality of trenches includes detecting when the passivation layer on the bottom of the trench having the Nth smallest width is removed by detecting a change in a waveform of an emission spectrum of the plasma using an emission spectrometer.

6. The method according to claim 5, wherein

the waveform represents an intensity of an emission peak derived from F radical or C⁺ ion.

7. The method according to claim 1, wherein

the forming of the plurality of trenches further includes a passivation layer removal step for removing the passivation layer on the bottom of the plurality of trenches by inducing oxygen plasma in the chamber and by applying the oxygen plasma to the wafer, and

the passivation layer removal step is performed after the passivation step and the etching step are repeated a plurality of times.

8. A method of manufacturing a semiconductor device comprising:

preparing a wafer having a silicon layer on which a mask having a plurality of openings is located, the plurality of openings having M different widths, where M is a positive integer more than one;

placing the wafer in a chamber; and

forming a plurality of trenches simultaneously in the silicon layer of the wafer through the mask, the plurality of trenches having M different widths defined by the plurality of openings of the mask, wherein

the forming of the plurality of trenches includes alternately and repeatedly performing a passivation step and an etching step,

the passivation step includes depositing a polymer passivation layer on a side wall and a bottom of the plurality of trenches by converting gas introduced in the chamber into plasma,

the etching step includes removing the passivation layer on the bottom of the plurality of trenches until the silicon layer is exposed to the bottom and applying reactive ion etching to the exposed silicon layer to increase a depth of the plurality of trenches,

the etching step further includes setting incident ion energy for the reactive ion etching to a predetermined energy value after a predetermined lapse time from when the passivation layer on the bottom of the trench having the smallest width is removed, and

the energy value prevents the passivation layer from being removed.

9. The method according to claim 8, wherein

the forming of the plurality of trenches includes performing a switch from the etching step to the passivation step when the passivation layer on a side wall of the trench having the smallest width is removed.

10. The method according to claim 8, wherein

the forming of the plurality of trenches includes detecting when the passivation layer on the bottom of the trench having the smallest width is removed by detecting a change in a waveform of an emission spectrum of the plasma using an emission spectrometer.

11. The method according to claim 10, wherein

the waveform represents an intensity of an emission peak derived from F radical or C⁺ ion.

12. The method according to claim 8, wherein

the forming of the plurality of trenches includes a passivation layer removal step for removing the passivation layer on the bottom of the plurality of trenches by inducing oxygen plasma in the chamber and by applying the oxygen plasma to the wafer, and

the passivation layer removal step is performed after the passivation step and the etching step are repeated a plurality of times.