Semiconductor device

• US 8,461,586 B2
• Filed: 07/01/2011
• Issued: 06/11/2013
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kato, Kiyoshi, Nagatsuka, Shuhei
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/175,542
• Publication Number:
  US 20120012837A1
• Time in Patent Office: 711 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t_a/t_b)×(∈_ra/∈_rb)<0.1, where t_a represents the thickness of the gate insulating layer, t_b represents the thickness of the insulating layer, ∈_ra represents the dielectric constant of the gate insulating layer, and ∈_rb represents the dielectric constant of the insulating layer.

Claims

1. A semiconductor device comprising:

a memory cell comprising;

a first transistor including;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and

a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region;

a second transistor including;

a second channel formation region;

a source electrode and a drain electrode which are electrically connected to the second channel formation region;

a second gate electrode over the second channel formation region; and

a second gate insulating layer between the second channel formation region and the second gate electrode; and

an insulating layer between the second channel formation region and one of the source region and the drain region,

wherein the first transistor and the second transistor overlap with each other at least partly, and

wherein the second gate insulating layer and the insulating layer satisfy a formula;

2. The semiconductor device according to claim 1, wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode.

3. The semiconductor device according to claim 1, wherein a capacitor is constituted by the second gate insulating layer, a conductive layer, and one of the source electrode and the drain electrode.

4. The semiconductor device according to claim 1,

wherein the first channel formation region includes a first semiconductor material,

wherein the second channel formation region include a second semiconductor material, and

wherein the first semiconductor material and the second semiconductor material are different from each other.

5. The semiconductor device according to claim 1, wherein the second channel formation region includes an oxide semiconductor.

6. A semiconductor device comprising:

a memory cell comprising;

a first transistor including;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and

a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region;

a second transistor including;

a second channel formation region;

a source electrode and a drain electrode which are electrically connected to the second channel formation region;

a second gate electrode over the second channel formation region; and

a second gate insulating layer between the second channel formation region and the second gate electrode; and

an insulating layer between the second channel formation region and one of the source region and the drain region,

wherein the first transistor and the second transistor overlap with each other at least partly, and

wherein the second gate insulating layer and the insulating layer satisfy a formula;

7. The semiconductor device according to claim 6, wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode.

8. The semiconductor device according to claim 6, wherein a capacitor is constituted by the second gate insulating layer, a conductive layer, and one of the source electrode and the drain electrode.

9. The semiconductor device according to claim 6,

wherein the first channel formation region includes a first semiconductor material,

wherein the second channel formation region include a second semiconductor material, and

wherein the first semiconductor material and the second semiconductor material are different from each other.

10. The semiconductor device according to claim 6, wherein the second channel formation region includes an oxide semiconductor.

11. A semiconductor device comprising:

a memory cell comprising;

a first transistor including;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer, wherein the first gate electrode overlaps with the first channel formation region; and

a source region and a drain region, wherein the first channel formation region is interposed between the source region and the drain region;

a second transistor including;

a second channel formation region;

a source electrode and a drain electrode which are electrically connected to the second channel formation region;

a second gate electrode over the second channel formation region; and

a second gate insulating layer between the second channel formation region and the second gate electrode; and

an insulating layer between the second channel formation region and one of the source region and the drain region,

wherein the first transistor and the second transistor overlap with each other at least partly,

wherein a part of the source electrode and a part of the drain electrode are provided over the second channel formation region, and

wherein the second gate insulating layer and the insulating layer satisfy a formula;

12. The semiconductor device according to claim 11, wherein the first gate electrode is electrically connected to one of the source electrode and the drain electrode.

13. The semiconductor device according to claim 11, wherein a capacitor is constituted by the second gate insulating layer, a conductive layer, and one of the source electrode and the drain electrode.

14. The semiconductor device according to claim 11,

wherein the first channel formation region includes a first semiconductor material,

wherein the second channel formation region include a second semiconductor material, and

wherein the first semiconductor material and the second semiconductor material are different from each other.

15. The semiconductor device according to claim 11, wherein the second channel formation region includes an oxide semiconductor.