Transistors, methods of manufacturing a transistor, and electronic devices including a transistor

• US 8,461,597 B2
• Filed: 08/11/2010
• Issued: 06/11/2013
• Est. Priority Date: 01/15/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Park, Jae-chul, Kim, Sang-wook, Park, Young-soo, Kim, Chang-jung
• Primary Examiner(s): Fulk, Steven J
• Application Number:
  US12/805,648
• Publication Number:
  US 20110175080A1
• Time in Patent Office: 1,035 Days
• Field of Search: 257/72, 257/E29.296, 438/164
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Transistors, methods of manufacturing a transistor, and electronic devices including a transistor are provided, the transistor includes a channel layer, a source and a drain respectively contacting opposing ends of the channel layer, a gate corresponding to the channel layer, a gate insulating layer between the channel layer and the gate, and a first passivation layer and a second passivation layer sequentially disposed on the gate insulating layer. The first passivation layer covers the source, the drain, the gate, the gate insulating layer and the channel layer. The second passivation layer includes fluorine (F).

Claims

1. A transistor, comprising:

a channel layer including an oxide semiconductor;

a source and a drain respectively contacting opposing ends of the channel layer;

a gate corresponding to the channel layer;

a gate insulating layer between the channel layer and the gate;

a first passivation layer covering the source, the drain, the gate, the gate insulating layer and the channel layer, wherein fluorine (F) is excluded from the first passivation layer; and

a second passivation layer including fluorine (F) on the first passivation layer, wherein the second passivation layer directly contacts all of the upper surface of the first passivation layer, and the first passivation layer is interposed between the second passivation layer and the source and the drain.

2. The transistor of claim 1, wherein the oxide semiconductor includes a ZnO-based oxide.

3. The transistor of claim 2, wherein the ZnO-based oxide is a complex oxide including at least one element selected from the group consisting of indium (In), aluminum (Al), gallium (Ga), titanium (Ti), tin (Sn), zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), chromium (Cr) and combinations thereof.

4. The transistor of claim 1, wherein the first passivation layer includes at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an organic material layer and combinations thereof.

5. The transistor of claim 1, wherein the second passivation layer includes at least one selected from the group consisting of an F-doped silicon oxide layer, an F-doped silicon nitride layer, an F-doped silicon oxynitride layer and combinations thereof.

6. The transistor of claim 1, wherein the first passivation layer has a thickness in a range of about 1000-Å

-to about 3000-Å

.

7. The transistor of claim 1, wherein the second passivation layer has a thickness in a range of about 100-Å

to about 3000-Å

.

8. The transistor of claim 1, wherein the gate insulating layer includes at least one layer selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a high-k dielectric material layer and combinations thereof.

9. The transistor of claim 1, wherein the gate insulating layer includes at least one selected from the group consisting of an F-doped silicon oxide layer, an F-doped silicon nitride layer, an F-doped silicon oxynitride layer, an F-doped high-k dielectric material layer and combinations thereof.

10. The transistor of claim 1, wherein the gate is above the channel layer.

11. The transistor of claim 1, wherein the gate is below the channel layer.

12. A flat panel display device, comprising:

the transistor according to claim 1.

13. The transistor of claim 1, wherein the second passivation layer and the channel layer do not contact each other.

14. A method of manufacturing a transistor, the method comprising:

forming a channel layer including an oxide semiconductor;

forming source and drain respectively contacting opposing ends of the channel layer;

forming a gate corresponding to the channel layer;

forming a gate insulating layer between the channel layer and the gate;

forming a first passivation layer that covers the source, the drain, the gate, the gate insulating layer and the channel layer, wherein fluorine (F) is excluded from the first passivation layer; and

forming a second passivation layer containing fluorine (F) on the first passivation layer, wherein the second passivation layer directly contacts all of the upper surface of the first passivation layer, and the first passivation layer is interposed between the second passivation layer and the source and the drain.

15. The method of claim 14, wherein the oxide semiconductor includes a ZnO-based oxide.

16. The method of claim 15, wherein the ZnO-based oxide is a complex oxide including at least one element selected from the group consisting of indium (In), aluminum (Al), gallium (Ga), titanium (Ti), tin (Sn), zirconium (Zr), hafnium (Hf), yttrium (Y), tantalum (Ta), chromium (Cr) and combinations thereof.

17. The method of claim 14, wherein forming the second passivation layer includes performing a chemical vapor deposition (CVD) method using a reaction gas including a fluorine (F)-containing first gas.

18. The method of claim 17, wherein the F-containing first gas includes at least one selected from the group consisting of CF₄, SF₆, CHF₃, F₂, C₂F₆, NF₃ and combinations thereof.

19. The method of claim 17, wherein the reaction gas further includes at least one of a silicon (Si)-containing second gas and a nitrogen (N)-containing third gas.

20. The method of claim 19, wherein the Si-containing second gas includes at least one selected from the group consisting of SiF₄, SiH₄, SiH₂ and combinations thereof.

21. The method of claim 19, wherein the N-containing third gas includes at least one selected from the group consisting of NH₃, N₂O, N₂, NO and combinations thereof.

22. The method of claim 17, wherein the F-containing first gas includes at least one of silicon (Si), nitrogen (N) and combinations thereof.

23. The method of claim 14, wherein the second passivation layer and the channel layer do not contact each other.